Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays最新文献_第7页

Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement 片上FPGA同步延迟测量的陷阱与权衡

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847334

Timothy Linscott, Benjamin Gojman, Raphael Rubin, A. DeHon

引用次数: 4

A Case for Work-stealing on FPGAs with OpenCL Atomics 基于OpenCL原子的fpga工作窃取案例

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847343

Nadesh Ramanathan, John Wickerson, F. Winterstein, G. Constantinides

引用次数: 36

Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs fpga的空间调试与无需重新编程的调试:fpga的片上调试

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847286

P. Shanker

{"title":"Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs","authors":"P. Shanker","doi":"10.1145/2847263.2847286","DOIUrl":"https://doi.org/10.1145/2847263.2847286","url":null,"abstract":"SmartFusion2 Family of FPGAs from MicroSemi introduces novel Silicon technology that enables minimally intrusive, spatial debug capabilities. Spatial debug concerns itself with observing and controlling sequential elements in the user?s Design Under Test (DUT) at an instant of time, i.e. in a specific clock cycle. This capability is made possible by the in-situ, always available probe network running at 50MHz in Smartfusion2. Observing and controlling DUT is less intrusive than conventional methods. Furthermore, no instrumentation and no re-programming of the FPGA device is required. This reduces the number of debug iterations (test re-runs) and accelerates design bring-up in the lab. This session showcases a technique to debug pseudo-static signals, i.e. sequential elements that remain static over a duration of time spanning many clock cycles of probe network (50MHz). Partial or entire set of sequential logic in the DUT can be read out via the JTAG or the SPI interface, while the DUT is running. This technique of observation is non-intrusive. A method to debug DUT using clock halting is presented. In such a method, the clock of the DUT is halted based on a trigger signal that is external or internal to the DUT. The trigger signal can be dynamically chosen without re-programming the device. Once the trigger fires, and clock is halted using a glitchless clock gate, any portion of the sequential logic in the DUT can be written to (altered) and then if required, the user clock can be gated ON to resume normal operation. Though somewhat intrusive, this technique of controlling hard to reach DUT states is invaluable in certain debug situations.","PeriodicalId":438572,"journal":{"name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122056138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Agile Co-Design for a Reconfigurable Datacenter 可重构数据中心的敏捷协同设计

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847287

Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, M. Haselman, S. Heil, K. Holohan, M. Humphrey, Tamás Juhász, P. Kaur, S. Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, J. Thong, Lisa Woods, Derek Chiou, D. Burger

引用次数: 2

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only) 基于新兴MTJ器件技术的随机自旋可编程门阵列(摘要)

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847317

Yu Bai, Mingjie Lin

{"title":"Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only)","authors":"Yu Bai, Mingjie Lin","doi":"10.1145/2847263.2847317","DOIUrl":"https://doi.org/10.1145/2847263.2847317","url":null,"abstract":"This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in FPGAs, our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure. Our mixed mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10x improvement in logic density, about 5x improvement in average net delay, and about 5x improvement in the critical path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.","PeriodicalId":438572,"journal":{"name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122638367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only) 基于可重复配置模块的FPGA本地互连测试(仅摘要)

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847309

Zhendi Yang, Jian Wang, Meng Yang, Jinmei Lai

引用次数: 1

SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing 基于三模冗余空间处理的LEON3软处理器SEU缓解与验证

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847278

M. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David Lee, J. Draper

{"title":"SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing","authors":"M. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David Lee, J. Draper","doi":"10.1145/2847263.2847278","DOIUrl":"https://doi.org/10.1145/2847263.2847278","url":null,"abstract":"Processors are an essential component in most satellite payload electronics and handle a variety of functions including command handling and data processing. There is growing interest in implementing soft processors on commercial FPGAs within satellites. Commercial FPGAs offer reconfigurability, large logic density, and I/O bandwidth; however, they are sensitive to ionizing radiation and systems developed for space must implement single-event upset mitigation to operate reliably. This paper investigates the improvements in reliability of a LEON3 soft processor operating on a SRAM-based FPGA when using triple-modular redundancy and other processor-specific mitigation techniques. The improvements in reliability provided by these techniques are validated with both fault injection and heavy ion radiation tests. The fault injection experiments indicate an improvement of 51× and the radiation testing results demonstrate an average improvement of 10×. Orbit failure rate estimations were computed and suggest that the TMR LEON3 processor has a mean-time to failure of over 76 years in a geosynchronous orbit.","PeriodicalId":438572,"journal":{"name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131058374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling 嵌入微通道流体冷却的三维fpga物理设计

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847275

Zhiyuan Yang, Ankur Srivastava

{"title":"Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling","authors":"Zhiyuan Yang, Ankur Srivastava","doi":"10.1145/2847263.2847275","DOIUrl":"https://doi.org/10.1145/2847263.2847275","url":null,"abstract":"Through Silicon Via (TSV) based 3D integration technology is a promising technology to increase the performance of FPGAs by achieving shorter global wire-length and higher logic density. However, 3D FPGAs also suffer from severe thermal problems due to the increase in power density and thermal resistance. Moreover, past work has shown that leakage power can account for 40% of the total power at current technology nodes and leakage power increases non-linearly with temperature. This intensifies the thermal problem in 3D FPGAs and more aggressive cooling methods such as micro-channel based fluidic cooling are required to fully exploit their benefits. The interaction between micro-channel heat sink design and the performance of a 3D FPGA is very complicated and a comprehensive approach is required to identify the optimal design of 3D FPGAs subject to thermo-electrical constraints. In this work, we propose an analysis framework for 3D FPGAs embedded with micro-channel-based fluidic cooling to study the impact of channel density on cooling and performance. According to our simulation results, we provide guidelines for designing 3D FPGAs embedded with micro-channel cooling and identify the optimal design for each benchmark. Compared to naive 3D FPGA designs which use fixed thermal heat sink, the optimal design identified using our framework can improve the operating frequency and energy efficiency by up to 80.3% and 124.0%.","PeriodicalId":438572,"journal":{"name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130980672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only) 知识就是力量:面向运行时优化的模块级感知(仅摘要)

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847316

James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, P. Cheung, G. Constantinides

{"title":"Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only)","authors":"James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, P. Cheung, G. Constantinides","doi":"10.1145/2847263.2847316","DOIUrl":"https://doi.org/10.1145/2847263.2847316","url":null,"abstract":"We propose the compile-time instrumentation of coexisting modules?IP blocks, accelerators, etc.?implemented in FPGAs. The efficient mapping of tasks to execution units can then be achieved, for power and/or timing performance, by tracking dynamic power consumption and/or timing slack online at module-level granularity. Our proposed instrumentation is transparent, thereby not affecting circuit functionality. Power and timing overheads have proven to be small and tend to be outweighed by the exposed runtime benefits. Dynamic power consumption can be inferred through the measurement of switching activity on indicative, frequently toggling nets. Online analysis is able to derive a live power breakdown by building and updating a model fed with per-module activity counts and system-wide power consumption. Such a model can be continuously refined and its use allows the tracking of unpredictable phenomena, including degradation. Online measurement of slack in critical (and near-critical) paths facilitates the safe erosion of static timing analysis-derived guardbands. This then enables the co-optimisation of power and timing performance under given external operating constraints, including those which change over time. Assuming functional compatibility, high-priority tasks would suit execution within modules with excess slack. This could be reduced via dynamic frequency scaling, thereby increasing throughput.","PeriodicalId":438572,"journal":{"name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132648878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Activity Aware Placement Approach For 3D FPGAs (Abstract Only) 一种3D fpga的活动感知放置方法(仅摘要)

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Pub Date : 2016-02-21 DOI: 10.1145/2847263.2847322

Girish Deshpande, D. Bhatia

{"title":"An Activity Aware Placement Approach For 3D FPGAs (Abstract Only)","authors":"Girish Deshpande, D. Bhatia","doi":"10.1145/2847263.2847322","DOIUrl":"https://doi.org/10.1145/2847263.2847322","url":null,"abstract":"In order to cope with increasing demand for higher logic densities and shrinking feature sizes, there has been a concerted effort by academia and industry towards the design of three dimensional integrated circuits (3D ICs). Various architectural approaches have been investigated over the past few years in order to realize functional 3D ICs. A majority of such research has been focused on devices such as memories, caches and other application specific circuits. Not much work has been done in the FPGA community on the exploration of 3D FPGAs both at the architectural and EDA levels. This work aims to look at placement methodologies and metrics for island style 3D FPGAs from a thermal perspective. The novelty of our approach lies in the fact that unlike previous related works on 3D FPGA placement which rely solely on wirelength and TSV (Through Silicon Via)-count minimization to evaluate placement, we propose a 3D placer that also takes into consideration, the transition density of each net to ensure a more thermally balanced spatial distribution of nets on the chip. This placement methodology tries to place nets which exhibit higher transition densities on the lower most layer of the FPGA. The lowest layer is typically closest to the heat sink and placing nets with higher switching activity on this layer will aid heat dissipation in a more effective manner and reduce hot spots on the chip. This placer was tested on a four layer 3D FPGA model using MCNC benchmarks and on average, around 40 % of high activity nets were placed on the lowest layer as compared to a placer that did not employ transition density based cost scaling during placement.","PeriodicalId":438572,"journal":{"name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0