An Activity Aware Placement Approach For 3D FPGAs (Abstract Only)

Abstract

In order to cope with increasing demand for higher logic densities and shrinking feature sizes, there has been a concerted effort by academia and industry towards the design of three dimensional integrated circuits (3D ICs). Various architectural approaches have been investigated over the past few years in order to realize functional 3D ICs. A majority of such research has been focused on devices such as memories, caches and other application specific circuits. Not much work has been done in the FPGA community on the exploration of 3D FPGAs both at the architectural and EDA levels. This work aims to look at placement methodologies and metrics for island style 3D FPGAs from a thermal perspective. The novelty of our approach lies in the fact that unlike previous related works on 3D FPGA placement which rely solely on wirelength and TSV (Through Silicon Via)-count minimization to evaluate placement, we propose a 3D placer that also takes into consideration, the transition density of each net to ensure a more thermally balanced spatial distribution of nets on the chip. This placement methodology tries to place nets which exhibit higher transition densities on the lower most layer of the FPGA. The lowest layer is typically closest to the heat sink and placing nets with higher switching activity on this layer will aid heat dissipation in a more effective manner and reduce hot spots on the chip. This placer was tested on a four layer 3D FPGA model using MCNC benchmarks and on average, around 40 % of high activity nets were placed on the lowest layer as compared to a placer that did not employ transition density based cost scaling during placement.