Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only)

Abstract

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in FPGAs, our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure. Our mixed mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10x improvement in logic density, about 5x improvement in average net delay, and about 5x improvement in the critical path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.