Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs

Abstract

SmartFusion2 Family of FPGAs from MicroSemi introduces novel Silicon technology that enables minimally intrusive, spatial debug capabilities. Spatial debug concerns itself with observing and controlling sequential elements in the user?s Design Under Test (DUT) at an instant of time, i.e. in a specific clock cycle. This capability is made possible by the in-situ, always available probe network running at 50MHz in Smartfusion2. Observing and controlling DUT is less intrusive than conventional methods. Furthermore, no instrumentation and no re-programming of the FPGA device is required. This reduces the number of debug iterations (test re-runs) and accelerates design bring-up in the lab. This session showcases a technique to debug pseudo-static signals, i.e. sequential elements that remain static over a duration of time spanning many clock cycles of probe network (50MHz). Partial or entire set of sequential logic in the DUT can be read out via the JTAG or the SPI interface, while the DUT is running. This technique of observation is non-intrusive. A method to debug DUT using clock halting is presented. In such a method, the clock of the DUT is halted based on a trigger signal that is external or internal to the DUT. The trigger signal can be dynamically chosen without re-programming the device. Once the trigger fires, and clock is halted using a glitchless clock gate, any portion of the sequential logic in the DUT can be written to (altered) and then if required, the user clock can be gated ON to resume normal operation. Though somewhat intrusive, this technique of controlling hard to reach DUT states is invaluable in certain debug situations.