Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only)

Abstract

We propose the compile-time instrumentation of coexisting modules?IP blocks, accelerators, etc.?implemented in FPGAs. The efficient mapping of tasks to execution units can then be achieved, for power and/or timing performance, by tracking dynamic power consumption and/or timing slack online at module-level granularity. Our proposed instrumentation is transparent, thereby not affecting circuit functionality. Power and timing overheads have proven to be small and tend to be outweighed by the exposed runtime benefits. Dynamic power consumption can be inferred through the measurement of switching activity on indicative, frequently toggling nets. Online analysis is able to derive a live power breakdown by building and updating a model fed with per-module activity counts and system-wide power consumption. Such a model can be continuously refined and its use allows the tracking of unpredictable phenomena, including degradation. Online measurement of slack in critical (and near-critical) paths facilitates the safe erosion of static timing analysis-derived guardbands. This then enables the co-optimisation of power and timing performance under given external operating constraints, including those which change over time. Assuming functional compatibility, high-priority tasks would suit execution within modules with excess slack. This could be reduced via dynamic frequency scaling, thereby increasing throughput.