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Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)最新文献

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A fast, simple router for the Data-Intensive Architecture (DIVA) system 一个快速，简单的路由器，用于数据密集型架构(DIVA)系统
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951617
C. Kang, J. Draper
{"title":"A fast, simple router for the Data-Intensive Architecture (DIVA) system","authors":"C. Kang, J. Draper","doi":"10.1109/MWSCAS.2000.951617","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951617","url":null,"abstract":"This paper presents a fast, simple router design for implementing the Red Rover algorithm for a bidirectional ring. This design is very suitable for the Data-Intensive Architecture (DIVA) system, a system which demonstrates the benefits of embedded DRAM technology, because of its high performance as well as simple architecture and low cost. The key attributes of this router are one clock node-to-node latency, high channel throughput, and simple hardware implementation. The router architecture employs short-cut FIFO data paths, which makes the router speed independent of the channel buffer size (in terms of flits). A prototype implementation of the router achieves a maximum channel bandwidth of 5.12 Gb/s and runs at 80 MHz using 3.3 V CMOS signaling in 0.5 /spl mu/m technology. This high throughput and low latency were achieved without resorting to the use of complex high-speed signaling technologies.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121756071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A convolution model and a cepstral filtering algorithm for the reduction of blocking artifacts 一种用于减少块伪影的卷积模型和倒谱滤波算法
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952831
N. Cho
{"title":"A convolution model and a cepstral filtering algorithm for the reduction of blocking artifacts","authors":"N. Cho","doi":"10.1109/MWSCAS.2000.952831","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952831","url":null,"abstract":"Proposes a convolution model and a cepstral filtering algorithm for reducing the blocking artifacts in compressed images and videos. Since each of the horizontal or vertical lines of the compressed image has abrupt changes at almost every 8th sample, images can be modeled as a convolution of the original sequence with an excitation signal of periodicity 8. Comparison of the cepstrums also shows that the multiples of 8th samples of the compressed signal's cepstrum usually have larger magnitudes than those of the original. The proposed filtering algorithm is to reduce the magnitudes of every 8th sample of the cepstrum, and disperse the reduced values to the neighboring samples. The algorithm is conducted in the cepstrum domain for reducing only the excitation signal which is the cause of blocking artifacts. Hence, the high frequency contents are not reduced by the postprocessing, whereas the conventional lowpass filtering blurs the image.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 500 MHz digital-to-analog converter with curve interpolation 一个500兆赫数模转换器与曲线插值
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951680
Hongwei Wang, C. Chan, C. Choy
{"title":"A 500 MHz digital-to-analog converter with curve interpolation","authors":"Hongwei Wang, C. Chan, C. Choy","doi":"10.1109/MWSCAS.2000.951680","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951680","url":null,"abstract":"This paper presents the design and measurement results of a curve-interpolated D/A. The curve-interpolated D/A has a maximum operating frequency of 500 MHz and a power consumption of 200 mw (at 500 MHz with 5V supply). The test results have indicated that the curve-interpolated D/A can relax the speed requirement of the A/Ds and DSPs by a factor of sixteen.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134077623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current mirror based folding amplifier 基于电流反射镜的折叠放大器
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951587
Yunchu Li, E. Sánchez-Sinencio
{"title":"Current mirror based folding amplifier","authors":"Yunchu Li, E. Sánchez-Sinencio","doi":"10.1109/MWSCAS.2000.951587","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951587","url":null,"abstract":"In this paper, a current mirror based folding amplifier is proposed. Compared to conventional differential-pair based voltage mode folding amplifier, this current mode folding amplifier is much easier to achieve ideal triangular-shape transfer characteristic curve. The proposed circuit can also operate at low power supply voltage.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131079807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Analysis of MPLS traffic engineering MPLS流量工程分析
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952816
Jong‐Moon Chung
{"title":"Analysis of MPLS traffic engineering","authors":"Jong‐Moon Chung","doi":"10.1109/MWSCAS.2000.952816","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952816","url":null,"abstract":"The upper limit of transmittable bandwidth doubles and sometimes quadruples every nine to twelve months. Already transmission of tens of tera bits-per-second over a single optical fiber is possible and matching data transferring topologies as well as improved system reliability are currently needed. Multiprotocol label switching (MPLS) has been emerging as the protocol of the future due to it's true \"multiprotocol architecture\" where it utilizes a simple label switching mechanism and provides quality of service (QoS) features through traffic engineering. Additionally, MPLS provides a solution to scalability and enables significant flexibility in routing. It can easily enable high quality end-to-end service features that are necessary in applications such as virtual private networks (VPN). These benefits of MPLS networking are made possible through traffic engineering. Currently, the constraint-based routing label distribution protocol (CR-LDP) and the resource reservation protocol (RSVP) are the signaling algorithms used for traffic engineering. In this paper, we investigate the signaling procedures of the CR-LDP and RSVP algorithms and discuss the appropriateness of the applications in MPLS traffic engineering networks. Based on network reliability and QoS reservation capabilities, CR-LDP was determined to be superior to RSVP signaling.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131170478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Iterated calculation of global implications and recursive learning in combinational equivalence checking 组合等价检验中全局蕴涵的迭代计算与递归学习
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952917
S. Reda, A. Wahba, A. Salem, M. Ghonaimy
{"title":"Iterated calculation of global implications and recursive learning in combinational equivalence checking","authors":"S. Reda, A. Wahba, A. Salem, M. Ghonaimy","doi":"10.1109/MWSCAS.2000.952917","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952917","url":null,"abstract":"Boolean satisfiability and recursive learning have been used in solving the combinational equivalence-checking problem. In this paper, we extend the recursive learning procedure and integrate it with global implications calculated in an iterative way to reduce the time needed for the solution. We also propose a variable ordering scheme to minimize the number of iterations needed to calculate the implications.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133377691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interaction of threshold voltage and mobility temperature dependencies applied to stabilization of current and voltage 阈值电压和迁移率温度依赖性的相互作用应用于电流和电压的稳定
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951390
I. Filanovsky, Su-Tarn Lim
{"title":"Interaction of threshold voltage and mobility temperature dependencies applied to stabilization of current and voltage","authors":"I. Filanovsky, Su-Tarn Lim","doi":"10.1109/MWSCAS.2000.951390","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951390","url":null,"abstract":"Mutual compensation of mobility and threshold voltage temperature variations may result in a zero temperature coefficient (ZTC) bias point of an MOS transistor. In this case the temperature dependence of the output voltage for a diode-connected transistor is a linear function of absolute temperature with the slope controlled by bias current. The paper describes application of this temperature dependence to stabilization of current and voltage in reference circuits. Examples of design for 0.18 /spl mu/m CMOS technology, and the circuit simulations are provided.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127782341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An EZW compressed image technique for calculating texture signatures 一种用于计算纹理特征的EZW压缩图像技术
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952828
B. Wilson, M. Bayoumi
{"title":"An EZW compressed image technique for calculating texture signatures","authors":"B. Wilson, M. Bayoumi","doi":"10.1109/MWSCAS.2000.952828","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952828","url":null,"abstract":"Traditional techniques for texture feature extraction needlessly consume valuable system resources by decompressing and storing the image data prior to processing. This paper presents a new technique for calculating mean deviation texture signatures directly from wavelet-compressed images. The technique reduces the overhead while maintaining accuracy. It offers a reduction in memory and computational costs by reducing and simplifying the calculations performed and by eliminating the storage of the reconstructed image.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115868863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Delay-sum beamforming using delta-sigma modulated inputs 使用δ - σ调制输入的延迟和波束形成
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951429
C.T. Weibel, G. Fischer
{"title":"Delay-sum beamforming using delta-sigma modulated inputs","authors":"C.T. Weibel, G. Fischer","doi":"10.1109/MWSCAS.2000.951429","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951429","url":null,"abstract":"This paper presents a novel approach for the realization of time-domain beamformers. The developed delay-sum beamformer concept utilizes delta-sigma data converters at the front end, which produce highly oversampled (single-bit) data streams. Therefore, no additional interpolation procedure is necessary. Furthermore, the simple one-bit data-format enables a multiplier free implementation of the shading coefficients. MATLAB simulations have demonstrated the functionality of the proposed concept. The presented hardware configuration is flexible and well suited for a VLSI implementation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"649 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116421193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of a CMOS current-steering DAC using state-space models 利用状态空间模型表征CMOS电流导向DAC
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952845
K.A. Andersson, J. Wikner
{"title":"Characterization of a CMOS current-steering DAC using state-space models","authors":"K.A. Andersson, J. Wikner","doi":"10.1109/MWSCAS.2000.952845","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952845","url":null,"abstract":"Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122040152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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