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Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)最新文献

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Constraints implementation for IQML and MODE direction-of-arrival estimators IQML和MODE到达方向估计器的约束实现
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-12-01 DOI: 10.1109/MWSCAS.2000.951479
C. A. Alves, R. F. Colares, A. Lopes
{"title":"Constraints implementation for IQML and MODE direction-of-arrival estimators","authors":"C. A. Alves, R. F. Colares, A. Lopes","doi":"10.1109/MWSCAS.2000.951479","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951479","url":null,"abstract":"The iterative quadratic maximum likelihood IQML and the method of direction estimation MODE are well known \"high resolution\" direction-of-arrival DOA estimation methods. Their solutions lead to an optimization problem with constraints. The usual linear constraint presents a poor performance for certain DOA values. This work proposes a new linear constraint applicable to both DOA methods and compares their performance with two others: unit norm and usual linear constraint. It is shown that the proposed alternative performs better than other constraints. The resulting computational complexity is also investigated.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123029036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fast electric load forecasting using neural networks 基于神经网络的电力负荷快速预测
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-12-01 DOI: 10.1109/MWSCAS.2000.952840
M. Lopes, C. R. Minussi, A. Lotufo
{"title":"A fast electric load forecasting using neural networks","authors":"M. Lopes, C. R. Minussi, A. Lotufo","doi":"10.1109/MWSCAS.2000.952840","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952840","url":null,"abstract":"The objective of this work is the development of a methodology for electric load forecasting based on a neural network. Here, the backpropagation algorithm with an adaptive process based on fuzzy logic is used. This methodology results in fast training, when compared to the conventional formulation of the backpropagation algorithm. Results are presented using data from a Brazilian electric company and the performance is very good for the proposal objective.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124075591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A high speed 3.3V current mode CMOS comparators with 10-b resolution 一种具有10b分辨率的3.3V电流型高速CMOS比较器
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-12-01 DOI: 10.1109/MWSCAS.2000.952925
J. Soldera, N. Oki
{"title":"A high speed 3.3V current mode CMOS comparators with 10-b resolution","authors":"J. Soldera, N. Oki","doi":"10.1109/MWSCAS.2000.952925","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952925","url":null,"abstract":"This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, /spl plusmn/0.5uA resolution and has fast response. This circuit was implemented with 0.8 /spl mu/m CMOS n-well process with area of 120 /spl mu/m /spl times/ 105 /spl mu/m and operates with 3.3V (/spl plusmn/1.65V).","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116976169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Noise reduction in speech signals using a TMS320C31 digital signal processor 使用TMS320C31数字信号处理器对语音信号进行降噪
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-12-01 DOI: 10.1109/MWSCAS.2000.951468
J. V. Filho, L. Marcal
{"title":"Noise reduction in speech signals using a TMS320C31 digital signal processor","authors":"J. V. Filho, L. Marcal","doi":"10.1109/MWSCAS.2000.951468","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951468","url":null,"abstract":"This paper describes a speech enhancement system (SES) based on a TMS320C31 digital signal processor (DSP) for real-time application. The SES algorithm is based on a modified spectral subtraction method and a new speech activity detector (SAD) is used. The system presents a medium computational load and a sampling rate up to 18 kHz can be used. The goal is to use it to reduce noise in an analog telephone line.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel iterative division algorithm over GF(2/sup m/) and its semi-systolic VLSI realization GF(2/sup m/)迭代除法的新算法及其半收缩VLSI实现
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951643
C. Hu, Chien Ming Wu, Ming-Der Shieh, Y. Hwang
{"title":"Novel iterative division algorithm over GF(2/sup m/) and its semi-systolic VLSI realization","authors":"C. Hu, Chien Ming Wu, Ming-Der Shieh, Y. Hwang","doi":"10.1109/MWSCAS.2000.951643","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951643","url":null,"abstract":"Extends the binary algorithm invented by J. Stein [1967] and proposes two iterative division algorithms in finite field GF(2/sup m/). Algorithm EBg exhibits faster convergence while algorithm EBd has reduced complexity in each iteration. A (semi-)systolic array is designed for algorithm EBd, resulting in an area-time complexity better than the best result known to date based on the extended Euclid algorithm.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124373886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Gain-controlled resistors in analysis of amplifiers featuring accurate input and output impedance 增益控制电阻在精确输入和输出阻抗放大器分析中的应用
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951437
I. Filanovsky
{"title":"Gain-controlled resistors in analysis of amplifiers featuring accurate input and output impedance","authors":"I. Filanovsky","doi":"10.1109/MWSCAS.2000.951437","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951437","url":null,"abstract":"An amplifier featuring accurate input and output impedance can be considered as a device that includes two models of gain controlled resistors. The models are introduced, and it is shown how they can be used in the analysis and design of such an amplifier. Then the analysis is applied to two-transistor amplifiers used in practice, and a new configuration is added. The relationship that should exist between passive elements of these amplifiers to obtain input and output matching is formulated for all three circuits.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114658718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Topological transition from magnetic networks to the electric equivalent ones when iron losses are present 当铁损耗存在时，从磁网络到电等效网络的拓扑转变
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952839
S. Leva, A. Morando
{"title":"Topological transition from magnetic networks to the electric equivalent ones when iron losses are present","authors":"S. Leva, A. Morando","doi":"10.1109/MWSCAS.2000.952839","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952839","url":null,"abstract":"After presenting, based on Cherry rule, the classical deduction of the electric equivalent network of a transformer magnetic circuit, the authors introduce the extension of this topological approach when hysteresis losses are present. Specific considerations related to the matrix properties associated to the use of ideal transformers are also given. The method can be extended to the rotating machinery analysis. This allows to deduce the hysteresis torque.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116859277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save adder cells 利用免进位加法器单元对算法优化中的时间和面积权衡进行了精确的探索
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951655
Youngtaek Kim, Taewhan Kim
{"title":"An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save adder cells","authors":"Youngtaek Kim, Taewhan Kim","doi":"10.1109/MWSCAS.2000.951655","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951655","url":null,"abstract":"Timing and area of circuits are two of the most important design criteria to be optimized in data path synthesis. Further, carry-save adder (CSA) cell has been proven to be one of the most effective hardware units in optimizing timing and area of the circuits. However, the prior approaches have only been concerned with the optimization of a single operation tree using CSAs, and have not been able to optimize multiple operation trees properly. This paper proposes a practical solution to the problem of an accurate exploration of trade-offs between timing and area in optimizing arithmetic circuit using CSAs. The application of the approach leads to finding a best CSA implementation of circuit in terms of both timing and area.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121021119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Robust transmission of MELP-compressed speech: a tale of two channels melp压缩语音的鲁棒传输:两个通道的故事
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952821
T. Fuja, D. Sridhara, D. Rahikka, J. Collura, T. Fazel
{"title":"Robust transmission of MELP-compressed speech: a tale of two channels","authors":"T. Fuja, D. Sridhara, D. Rahikka, J. Collura, T. Fazel","doi":"10.1109/MWSCAS.2000.952821","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952821","url":null,"abstract":"This paper considers the transmission of speech compressed using the US federal standard 2400 bps compression algorithm. Two different kinds of communication channels are considered - a noisy channel characterized by fading and additive white Gaussian noise, and an ATM channel subject to cell loss. Two different error control strategies are applied to these two channels. For the noisy channel, standard convolutional codes are employed with a channel decoder \"tuned\" to exploit the residual redundancy inherent in the compressed bitstream; considerable coding gain is obtained with this approach compared to the standard decoder that does not exploit residual redundancy. For the lossy channel, Reed-Solomon codes are used with erasure decoding to recover lost cells; it is shown that a modest investment in interleaving and redundancy can yield near-noiseless performance even when the channel is subject to cell loss as high as 10-15%.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-cost jitter measurement technique for phase-locked loops 低成本锁相环抖动测量技术
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.952912
R. Voorakaranam, A. Chatterjee
{"title":"Low-cost jitter measurement technique for phase-locked loops","authors":"R. Voorakaranam, A. Chatterjee","doi":"10.1109/MWSCAS.2000.952912","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952912","url":null,"abstract":"A new low-cost technique for jitter measurement of phase-locked loops (PLLs) is described. The proposed technique can be applied to PLLs whose jitter is predominantly due to power supply noise. Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost tester instrumentation. By modulating the supply voltage to the PLL and noting that PLL jitter is extremely sensitive to power supply variations, it is possible to introduce significant jitter into the PLL output which can be measured using a low-cost tester During production test, a regression model is used to predict the inherent PLL jitter from the measurement of power supply induced jitter.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125776739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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