An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save adder cells

Abstract

Timing and area of circuits are two of the most important design criteria to be optimized in data path synthesis. Further, carry-save adder (CSA) cell has been proven to be one of the most effective hardware units in optimizing timing and area of the circuits. However, the prior approaches have only been concerned with the optimization of a single operation tree using CSAs, and have not been able to optimize multiple operation trees properly. This paper proposes a practical solution to the problem of an accurate exploration of trade-offs between timing and area in optimizing arithmetic circuit using CSAs. The application of the approach leads to finding a best CSA implementation of circuit in terms of both timing and area.