{"title":"Delay-sum beamforming using delta-sigma modulated inputs","authors":"C.T. Weibel, G. Fischer","doi":"10.1109/MWSCAS.2000.951429","DOIUrl":null,"url":null,"abstract":"This paper presents a novel approach for the realization of time-domain beamformers. The developed delay-sum beamformer concept utilizes delta-sigma data converters at the front end, which produce highly oversampled (single-bit) data streams. Therefore, no additional interpolation procedure is necessary. Furthermore, the simple one-bit data-format enables a multiplier free implementation of the shading coefficients. MATLAB simulations have demonstrated the functionality of the proposed concept. The presented hardware configuration is flexible and well suited for a VLSI implementation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"649 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.951429","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a novel approach for the realization of time-domain beamformers. The developed delay-sum beamformer concept utilizes delta-sigma data converters at the front end, which produce highly oversampled (single-bit) data streams. Therefore, no additional interpolation procedure is necessary. Furthermore, the simple one-bit data-format enables a multiplier free implementation of the shading coefficients. MATLAB simulations have demonstrated the functionality of the proposed concept. The presented hardware configuration is flexible and well suited for a VLSI implementation.