2008 9th International Conference on Solid-State and Integrated-Circuit Technology最新文献_第7页

Design and realization of a new compact branch-line coupler using defected ground structure 采用缺陷接地结构的新型紧凑型支路耦合器的设计与实现

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734818

Huaming Wang, Xueguan Liu, Wenfeng Cai, Hongfang Cao

引用次数: 10

Mask synthesis for 65nm SRAM manufacturing using gradient-based Inverse Lithography Technology (ILT) 基于梯度逆光刻技术(ILT)的65nm SRAM掩膜合成

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4735024

Wei Xiong, Jinyu Zhang, M. Tsai, Yan Wang, Zhiping Yu

引用次数: 0

Crest factor reduction and digital pre-distortion for wireless RF power amplifier optimization 用于无线射频功率放大器优化的波峰因数降低和数字预失真

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734813

T. Miracco

引用次数: 5

Piezoresistive sensor of short- and long- channel MOSFETs on (100) silicon 短沟道和长沟道mosfet的压阻式传感器

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4735053

W. Chang, Jian-an Lin, W. Yeh

引用次数: 0

Fabrication of improved FD SOIMOSFETs for suppressing edge effect 用于抑制边缘效应的改进FD somosfet的制造

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734514

Ning-Juan Wang, Ning Li, Zhong-li Liu, Fang Yu, Guohua Li

引用次数: 1

Fabrication and characteristics of Germanium-On-Insulator substrates 绝缘子上锗基板的制备及其特性

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734626

Hai-Yan Jin, E.Z. Liu, N. Cheung

{"title":"Fabrication and characteristics of Germanium-On-Insulator substrates","authors":"Hai-Yan Jin, E.Z. Liu, N. Cheung","doi":"10.1109/ICSICT.2008.4734626","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734626","url":null,"abstract":"The fabrication of Germanium-On-Insulator (GeOI) by wafer bonding and ion-cut approach was investigated. With cyclic HF/DIW cleaning and N2 plasma surface activation, large-area layer transfer of GeOI substrates was realized by ion-cut processes with bulk Ge wafer as the donor wafer. The GeOI substrates are thermally stable up to 550°C annealing and surface roughness can be smoothed down to 0.3 nm RMS by Chemical Mechanical Planarization (CMP). After surface polishing, Epi-Ge on Si wafer can also be used as the donor wafer to realize layer transfer. Four-probe configuration Pseudo-MOSFET was employed to characterize the electrical properties of the transferred Ge and the Ge/SiO2 bonding interface. At Ge/SiO2 interface, GeOI substrates show both accumulation and inversion conduction modes. High-temperature forming gas annealing in the vicinity of 500°C¿600°C has shown the best carrier mobilities, with the interface trap density and interface fixed charge density as low as 1010/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/V-s, which is higher than that of silicon (300 cm2/V-s) at the same doping concentration level.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"17 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Current status and possibilities of wafer-bonding-based SOI technology in 45nm or below CMOS LSIs 45纳米及以下CMOS lsi中基于晶圆键合的SOI技术的现状和可能性

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734637

M. Yoshimi, D. Delpra, I. Cayrefourcq, G. Celler, C. Mazure, B. Aspar

引用次数: 3

A 65μA 8MHz On-Chip Oscillator with LDO regulator for low-power handheld SoC applications 带LDO稳压器的65μA 8MHz片上振荡器，适用于低功耗手持SoC应用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734964

J. Day, P. Vulpoiu, D. Johnson, J. Julich, D. Lie

引用次数: 1

Low-power hardware implementation of ECC processor suitable for low-cost RFID tags 低功耗硬件实现的ECC处理器适用于低成本RFID标签

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734876

Peng Luo, Xinan Wang, Jun Feng, Ying Xu

{"title":"Low-power hardware implementation of ECC processor suitable for low-cost RFID tags","authors":"Peng Luo, Xinan Wang, Jun Feng, Ying Xu","doi":"10.1109/ICSICT.2008.4734876","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734876","url":null,"abstract":"RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper we propose a novel ALU architecture for ECC processor on tags. By specially restructured the conventional mathematical expressions of Montgomery algorithm, the ALU operation of point multiplication in our design is reduced by nearly 47%. Also, various multipliers, such as bit-serial multiplier, digit-serial multiplier and the divided algorithm are adopted to balance between power consumption and speed. To attain ultra low power consumption, other techniques, such as finite state machines (FSM) optimization, clock gating, pipelining operations and low-power target library are used in the design. The area of the ECC processor is equal to 16.9 k gates equivalents. It performs an elliptic curve point multiplication in 36174 clock cycles and has a power consumption of 6.607 ¿W at 1.28 MHz using TSMC 0.18 ¿m low-voltage cell library.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Gradual Ge1−xSix/Si heteronanocrystals based non-volatile floating gate memory device with asymmetric tunnel barriers 基于非对称隧道势垒的渐进式Ge1−xSix/Si异质晶体非易失性浮栅存储器件

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734701

Jin Lu, Guangli Wang, Yubin Chen, Z. Zuo, Yi Shi, L. Pu, Youdou Zheng

引用次数: 0