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Efficient FPGA implementation of modified DWT for JPEG2000 基于JPEG2000的改进DWT的高效FPGA实现
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4735007
Jie Guo, Keyan Wang, Chengke Wu, Yunsong Li
{"title":"Efficient FPGA implementation of modified DWT for JPEG2000","authors":"Jie Guo, Keyan Wang, Chengke Wu, Yunsong Li","doi":"10.1109/ICSICT.2008.4735007","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735007","url":null,"abstract":"An efficient implementation of discrete wavelet transform (DWT) in JPEG2000 is designed with low memory and high pipeline architecture. Considering the limited dynamic range of wavelet coefficients, a modified scheme of integer-to-integer discrete wavelet transform based on fixed-point manipulation is proposed by preserving efficiently fractions of coefficients in lifting steps. This scheme ensures higher computational precision in DWT and accordingly improves the compression quality. The corresponding line-based FPGA lifting scheme is put forward from hardware perspective. In a parallel way, transform can be row-wise and column-wise executed. Prototyped onto Xilinx Virtex-II FPGA, the proposed architecture requires fewer resources and memory accesses, but reaches a higher processing throughput. Experimental results provide parameters as follows. For an image with resolution 1024×1024, the inputting sampling is up to 61 Mpixels/s when DWT is working at the clock of 65 MHz. Internal memory of only 5 rows is required for the 9/7 filter to perform one-level 2-D decomposition. The completion of multi-level DWT is within the time T that an image is transmitted in line order.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132754586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-input and low-output impedance voltage-mode universal biquadratic filter using FDCCIIs 采用fdccii的高输入低输出阻抗电压型通用双二次型滤波器
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734904
Hua-Pin Chen, Yi-Zhen Liao
{"title":"High-input and low-output impedance voltage-mode universal biquadratic filter using FDCCIIs","authors":"Hua-Pin Chen, Yi-Zhen Liao","doi":"10.1109/ICSICT.2008.4734904","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734904","url":null,"abstract":"A novel high-input and low-output impedance voltage-mode universal filter with three inputs and single output employing two fully differential current conveyors, two resistors, and two capacitors is proposed. The proposed configuration can realize all the five standard biquadratic filter functions. It maintains the following advantages: (i) employment of only two current conveyors, (ii) employment of only grounded capacitors, (iii) employment of only grounded resistors, (iv) high-input and low-output impedance, (v) no need to employ inverting type input signals, (vi) no need to impose component choice conditions to realize specific filtering functions, and (vii) low active and passive sensitivity performances.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123186462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A PLL-based current-mode PWM circuit suitable for current-mode controlled techniques 一种基于锁相环的电流型PWM电路，适用于电流型控制技术
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734963
Yeong-Tsair Lin, Chi-Cheng Wu, Jia-Long Wu, M. Jen, Dong-Shiuh Wu, Huan-Ren Cheng
{"title":"A PLL-based current-mode PWM circuit suitable for current-mode controlled techniques","authors":"Yeong-Tsair Lin, Chi-Cheng Wu, Jia-Long Wu, M. Jen, Dong-Shiuh Wu, Huan-Ren Cheng","doi":"10.1109/ICSICT.2008.4734963","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734963","url":null,"abstract":"A wide-range current-mode pulse-width modulation circuit for current-mode controlled techniques is presented in this paper. The proposed circuit has been designed and implemented using 0.35-¿m CMOS 2P4M process. The core die size is around 95×115 ¿m2 . The experimental results show that the variation of the output frequency within ±0.25%. The linear range of input current is from 114 to 297 ¿A , and corresponding duty cycle of pulse-width output is from 2.5% to 93.5%.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131755515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analog/RF design techniques for high performance nanoelectronic on-chip interconnects 用于高性能纳米电子片上互连的模拟/射频设计技术
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734936
Bao Liu
{"title":"Analog/RF design techniques for high performance nanoelectronic on-chip interconnects","authors":"Bao Liu","doi":"10.1109/ICSICT.2008.4734936","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734936","url":null,"abstract":"On-chip interconnects form the bottleneck of VLSI system performance. As technology progresses, VLSI on-chip interconnects encounter increasingly significant challenges, such as (1) signal attenuation and (2) crosstalk coupling. This paper proposes two analog/RF design techniques for high performance nanoelectronic on-chip interconnects: (1) application of distributed amplifiers for signal attenuation compensation by reducing interconnect effective resistance, and (2) application of bandpass filters for noise immunity in a frequency separated VLSI on-chip communication system. HSPICE-RF simulation results in 65 nm CMOS technology verify that the proposed analog/RF design techniques achieve improved performance and reliability for high performance nanoelectronic on-chip interconnects.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131846795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Contact Block Reduction method for ballistic quantum transport with semi-empirical sp3d5s* tight binding band models 基于半经验sp3d5s*紧束缚带模型的弹道量子输运接触块缩减方法
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734543
H. Ryu, Gerhard Klimeck
{"title":"Contact Block Reduction method for ballistic quantum transport with semi-empirical sp3d5s* tight binding band models","authors":"H. Ryu, Gerhard Klimeck","doi":"10.1109/ICSICT.2008.4734543","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734543","url":null,"abstract":"The utility of the Contact Block Reduction method (CBR) to find the retarded Green¿s function for ballistic quantum devices with semi-empirical tight binding band (TB) models is discussed. This work shows that the original method needs several modifications to be used with TB models. In the common case where two contacts are used for transport in quantum wires, our approach computes the transmission coefficients with much less computing load than the state-of-the-art Recursive Green¿s Function (RGF) algorithm.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115398678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Resistive switching behaviors and mechanism of transition metal oxides-based memory devices 基于过渡金属氧化物的存储器件的电阻开关行为和机制
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734696
J. Kang, B. Sun, B. Gao, N. Xu, X. Sun, L.F. Liu, Y. Wang, X.Y. Liu, R. Han, Y. Wang
{"title":"Resistive switching behaviors and mechanism of transition metal oxides-based memory devices","authors":"J. Kang, B. Sun, B. Gao, N. Xu, X. Sun, L.F. Liu, Y. Wang, X.Y. Liu, R. Han, Y. Wang","doi":"10.1109/ICSICT.2008.4734696","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734696","url":null,"abstract":"In this paper, the characteristics and mechanism of the transition metal oxide (TMO) based resistive switching memory (RRAM) devices were addressed. The results show that doping in oxide matrix materials, electrode material, and operating mode of the set/reset process may significantly affect the resistive switching behaviors of RRAM devices. Optimizing the dopants and matrix materials, electrode materials, device structure, and operating modes and understanding the related mechanisms are required to achieve the excellent device performance of TMO-based RRAM for the memory application. A unified physical model, based on the electron hopping transport between oxygen vacancies along the conductive filament paths, is used to explain and describe the resistive switching behaviors of the TMO based RRAM devices.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124159521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of the turn-on characteristics of poly-silicon thin-film transistors with considering kink effect 考虑扭结效应的多晶硅薄膜晶体管导通特性建模
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734527
Bin Li, Ting Chen, Xueren Zheng
{"title":"Modeling of the turn-on characteristics of poly-silicon thin-film transistors with considering kink effect","authors":"Bin Li, Ting Chen, Xueren Zheng","doi":"10.1109/ICSICT.2008.4734527","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734527","url":null,"abstract":"A semi-empirical analytical model of the turn-on characteristics of poly-silicon thin-film transistor (TFT) with considering kink effect is presented based on the physical characteristics of poly-silicon thin film. With reference to the approach of modeling the kink effect in SOI devices and considering the grain boundaries in poly-silicon thin film, the dc characteristics of poly-silicon TFT are simulated, including drain induced grain boundary lowering (DIGBL) effect, impact ionization, floating body effect, parasitic bipolar transistor (PBT) effect, etc. The simulation results show a good agreement with the experimental data.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124543954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation and fabrication of the SiC-based clamped-clamped filter 基于sic的箝位-箝位滤波器的仿真与制作
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4735088
Y. Zhao, Jin Ning, Guosheng Sun, Xingfang Liu, Liangchen Wang, Gang Ji, Lei Wang, Wanshun Zhao, Jinmin Li, Fuhua Yang
{"title":"Simulation and fabrication of the SiC-based clamped-clamped filter","authors":"Y. Zhao, Jin Ning, Guosheng Sun, Xingfang Liu, Liangchen Wang, Gang Ji, Lei Wang, Wanshun Zhao, Jinmin Li, Fuhua Yang","doi":"10.1109/ICSICT.2008.4735088","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735088","url":null,"abstract":"In this paper, the SiC-based clamped-clamped filter was designed and fabricated. The filter was composed of two clamped-clamped beam micromechanical resonators coupled by a spring coupling beam. Structural geometries, including the length and width of the resonator beam and coupling beam, were optimized by simulation for high frequency and high Q, under the material properties of SiC. The vibrating modes for the designed filter structure were analyzed by finite element analysis (FEA) method. For the optimized structure, the geometries of resonator beams and coupling beams, as well as the coupling position, the SiC-based clamped-clamped filter was fabricated by surface micromaching technology.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114525987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of ultra-high-speed 10-bit D/A converter 超高速10位数模转换器的设计
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734954
G. Yan, D. Fu, Jun Liu, Zhou Yu
{"title":"Design of ultra-high-speed 10-bit D/A converter","authors":"G. Yan, D. Fu, Jun Liu, Zhou Yu","doi":"10.1109/ICSICT.2008.4734954","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734954","url":null,"abstract":"In this paper, an ultra-high-speed, differential current-steering mode 10-bit D/A converter is presented. The converter consists of 8-channel time division multiplexer, 5-31 ¿thermometer¿ decoder, fast current conversion switch, constant current source array, and other units, is processed in 0.35 ¿m SiGe BiCMOS standard process technology, and has a data fresh rate of up to 1 GSPS. First, the circuit principle and the structure and design methodology of different units are described. Then, the simulation results of circuit are given. Finally, 10-bit D/A converter are tested and analyzed. The results show that the 10-bit D/A converter features the high resolution, the fast speed, and the high universality.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The design, fabrication and characterization of GaAs-based RTT with groove and self-aligned Schottky gate structure 具有沟槽和自对准肖特基栅结构的gaas基RTT的设计、制造和表征
2008 9th International Conference on Solid-State and Integrated-Circuit Technology Pub Date : 2008-12-30 DOI: 10.1109/ICSICT.2008.4734594
Wei-lian Guo, P. Niu, Xiao-yun Li, Chang-yun Miao, Wei Wang, Xin Yu, Yaoyao Shang, Zhen Feng, Guoping Tian, Yali Li, Yongqiang Liu, Mingwen Yuan, Xiao-Bai Li
{"title":"The design, fabrication and characterization of GaAs-based RTT with groove and self-aligned Schottky gate structure","authors":"Wei-lian Guo, P. Niu, Xiao-yun Li, Chang-yun Miao, Wei Wang, Xin Yu, Yaoyao Shang, Zhen Feng, Guoping Tian, Yali Li, Yongqiang Liu, Mingwen Yuan, Xiao-Bai Li","doi":"10.1109/ICSICT.2008.4734594","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734594","url":null,"abstract":"In this paper, the design of material structure and device structure , fabrication processing and characterization on GaAs based Resonant Tunneling Transistor (RTT) with groove and self-aligned gate structure have been described completely and systematically .The experimental results measured from our fabricated RTT show that : the maximum value of Peak to Valley Current Ratio (PVCR) is 46, the transconductance gm is in a range of 1.3~8.0 ms, the cutoff frequency fTgm and speed index S are 1.59 GHz and 13.5 ps/V respectively .","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115052520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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