Current status and possibilities of wafer-bonding-based SOI technology in 45nm or below CMOS LSIs

Abstract

The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT, DSB), dynamic threshold voltage control by back-biasing (UT-BOX SOI), capacitor-less DRAM, etc., are promising options that can bring a breakthrough and continue proper scaling. Also, circuit layer transfer technology applied to back-side illumination of CMOS imager is presented, as a technology giving linkage with future 3D-integration of LSI system.