Jin Lu, Guangli Wang, Yubin Chen, Z. Zuo, Yi Shi, L. Pu, Youdou Zheng
{"title":"基于非对称隧道势垒的渐进式Ge1−xSix/Si异质晶体非易失性浮栅存储器件","authors":"Jin Lu, Guangli Wang, Yubin Chen, Z. Zuo, Yi Shi, L. Pu, Youdou Zheng","doi":"10.1109/ICSICT.2008.4734701","DOIUrl":null,"url":null,"abstract":"The gradual Ge1-xSix/Si heteronanocrystals on ultra thin SiO2 were fabricated to form the metal-oxide-semiconductor (MOS) memory structure with asymmetric tunnel barriers through combining self-assembled growth and selective chemical etching technique. Charge storage characteristics in such memory structure have been investigated by using capacitance-voltage measurements. The observations demonstrate that the holes reach a longer retention time even with an ultra thin tunnel oxide, owing to the high band offset at the valence band between Ge and Si.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Gradual Ge1−xSix/Si heteronanocrystals based non-volatile floating gate memory device with asymmetric tunnel barriers\",\"authors\":\"Jin Lu, Guangli Wang, Yubin Chen, Z. Zuo, Yi Shi, L. Pu, Youdou Zheng\",\"doi\":\"10.1109/ICSICT.2008.4734701\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The gradual Ge1-xSix/Si heteronanocrystals on ultra thin SiO2 were fabricated to form the metal-oxide-semiconductor (MOS) memory structure with asymmetric tunnel barriers through combining self-assembled growth and selective chemical etching technique. Charge storage characteristics in such memory structure have been investigated by using capacitance-voltage measurements. The observations demonstrate that the holes reach a longer retention time even with an ultra thin tunnel oxide, owing to the high band offset at the valence band between Ge and Si.\",\"PeriodicalId\":436457,\"journal\":{\"name\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"volume\":\"105 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2008.4734701\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gradual Ge1−xSix/Si heteronanocrystals based non-volatile floating gate memory device with asymmetric tunnel barriers
The gradual Ge1-xSix/Si heteronanocrystals on ultra thin SiO2 were fabricated to form the metal-oxide-semiconductor (MOS) memory structure with asymmetric tunnel barriers through combining self-assembled growth and selective chemical etching technique. Charge storage characteristics in such memory structure have been investigated by using capacitance-voltage measurements. The observations demonstrate that the holes reach a longer retention time even with an ultra thin tunnel oxide, owing to the high band offset at the valence band between Ge and Si.