2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)最新文献_第4页

Commutation for Functions of Small Arity Over a Finite Set 有限集上小幂函数的交换

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00023

Hajime Machida, I. Rosenberg

引用次数: 1

One Class of Maximal Binary Monomials 一类极大二元单项式

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00022

Hajime Machida, J. Pantović

引用次数: 0

Realization of Arithmetic Operators Based on Stochastic Number Frequency Signal Representation 基于随机数字频率信号表示的算术算子的实现

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00045

M. M. A. Taha, M. Perkowski

引用次数: 3

Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter 基于多电压/电流变换器的低功耗mtj真随机数发生器设计

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00035

Shogo Mukaida, N. Onizawa, T. Hanyu

引用次数: 3

Algebra of Transient States of Postan Signals 邮政信号暂态代数

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00046

Maciej Rudziecki

引用次数: 2

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor 一种三元权值二值输入卷积神经网络:在嵌入式处理器上的实现

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00038

H. Yonekawa, Shimpei Sato, Hiroki Nakahara

{"title":"A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor","authors":"H. Yonekawa, Shimpei Sato, Hiroki Nakahara","doi":"10.1109/ISMVL.2018.00038","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00038","url":null,"abstract":"In image recognition, techniques using a convolutional neural network (CNN) have been extensively studied and are widely used in various applications, such as a handwritten character recognition, a face recognition, a scene determination, and an object recognition. It has an enormous amount of computational complexity and internal parameters, and it is often implemented in high-performance GPUs. However, the embedded system requires real-time image recognition with a low-power consumption. In such systems, a binarized CNN has been proposed for the embedded system. It can achieve efficient implementation by restricting the values that the parameters inside CNN treating -1 and +1, and low bit precision of operations and memory. In the paper, we extend to a ternary weight binary input CNN to further increase its performance with a low-performance embedded processor. In the ternarized CNN, values that internal weight can take -1, +1 and 0, where zero weight can be realized by a skip computation. Since the number of possible states of the ternarized CNN is larger than that of the binarized CNN, high recognition accuracy can be obtained. Furthermore, we study an optimal training algorithm in the ternarized CNN and show the results by computer experiment. Comparison with the binarized CNN, as for the ARM processor, the ternary weight CNN was 8.13 times faster than the binary weight one.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115230294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

On a Memory-Based Realization of Sparse Multiple-Valued Functions 基于记忆的稀疏多值函数实现

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00017

Tsutomu Sasao

引用次数: 2

Logic Design Using Memristors: An Emerging Technology 使用忆阻器的逻辑设计:一项新兴技术

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00029

S. Shirinzadeh, K. Datta, R. Drechsler

引用次数: 7

Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices 超越位元:使用多位元多位元FDSOI元件的第四纪FPGA架构

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00015

S. Chaudhuri

引用次数: 3

Synthesis of Multi-valued Literal Using Lukasiewicz Logic 用Lukasiewicz逻辑综合多值文字

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-01 DOI: 10.1109/ISMVL.2018.00043

A. Surhonne, Debjyoti Bhattacharjee, A. Chattopadhyay

{"title":"Synthesis of Multi-valued Literal Using Lukasiewicz Logic","authors":"A. Surhonne, Debjyoti Bhattacharjee, A. Chattopadhyay","doi":"10.1109/ISMVL.2018.00043","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00043","url":null,"abstract":"The synthesis of multi-valued combinational functions is well-studied topic, albeit less compared to the synthesis of two-valued logic families. The synthesis of multi-valued functions consists of bi-decomposition or functional decomposition of the given target function to obtain a multilevel network comprising of min and max gates. Synthesis tools, such as YADE and those based on Multiple-Valued Decision Diagrams make the implicit assumption regarding the availability of literals or CASE operator, while focusing on the optimization of the logic network solely based on the min and max gates. However, a literal cannot be assumed to exist as a primitive in a multi-valued logic system and therefore, renders it difficult for one to directly apply the existing synthesis flows in practical settings [1]. We address this important gap in MVL synthesis flows. Our target multivalued logic is £ukasiewicz logic, which supports implication and negation. We derive literals and CASE operators using these primitives, and propose a heuristic algorithm to synthesize it automatically. Our techniques are implemented as an extension in the YADE tool. Our experimental studies on a wide range of benchmarks reveal that an average overhead of 216% in terms of number implication gates, along with 55% increase in the number of levels is encountered, in contrast to a synthesis flow that assumes existence of literals.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5