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2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)最新文献

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Saturated Models in Mathematical Fuzzy Logic 数学模糊逻辑中的饱和模型
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-10-23 DOI: 10.1109/ISMVL.2018.00034
Guillermo Badia, C. Noguera
{"title":"Saturated Models in Mathematical Fuzzy Logic","authors":"Guillermo Badia, C. Noguera","doi":"10.1109/ISMVL.2018.00034","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00034","url":null,"abstract":"This paper considers the problem of building saturated models for first-order graded logics. We define types as pairs of sets of formulas in one free variable which express properties that an element is expected, respectively, to satisfy and to falsify. We show, by means of an elementary chains construction, that each model can be elementarily extended to a saturated model where as many types as possible are realized. In order to prove this theorem we obtain, as by-products, some results on tableaux (understood as pairs of sets of formulas) and their consistency and satisfiability, and a generalization of the Tarski--Vaught theorem on unions of elementary chains.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129682316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Energy-Efficient Quaternary Serial Adder for Nanoelectronics 一种节能的纳米电子学第四纪串行加法器
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-07-19 DOI: 10.1109/ISMVL.2018.00016
Shima Sedighiani, A. Kazemi
{"title":"An Energy-Efficient Quaternary Serial Adder for Nanoelectronics","authors":"Shima Sedighiani, A. Kazemi","doi":"10.1109/ISMVL.2018.00016","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00016","url":null,"abstract":"Increased power consumption of scaling Complementary Metal Oxide Semiconductor (CMOS) technology and the limitations of binary communication have led to the consideration of non-silicon multiple-valued logic (MVL) circuits. The unique properties of Carbon Nanotube Field Effect Transistors (CNTFETs) in circuit design, such as the capability of setting the desired threshold voltage by adjusting the CNT diameters and the ballistic transport of carriers, make it possible to achieve an effective solution to improve energy efficiency and speed. Quaternary is the closest radix to the optimum (e=2.718) that has the advantage of easy communication with binary logic circuits. This study presents an efficient design of a quaternary serial adder based on CNTFETs. The design exploits an existing high-performance full adder and improves the carry propagation. Simulation results confirm that the proposed quaternary serial adder uses on average 57.8% of the power such an adder requires based on the current state-of-the-art quaternary full adders.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114576189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
CNOT-Measure Quantum Neural Networks 测量量子神经网络
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-07-19 DOI: 10.1109/ISMVL.2018.00040
M. Lukac, Kamila Abdiyeva, M. Kameyama
{"title":"CNOT-Measure Quantum Neural Networks","authors":"M. Lukac, Kamila Abdiyeva, M. Kameyama","doi":"10.1109/ISMVL.2018.00040","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00040","url":null,"abstract":"Various models of quantum neural networks exist imitating the powerful class of machine learning algorithms, widely applied and used in many of intelligent systems and applications. While comparative models of quantum neural networks exist, their computational complexity might require specific unitary transforms for simulating the activation function of the cell, simulation of continuous processes for learning or adding a large amount of ancilla qubits. In order to solve some of these problems, we present a quantum neural network model called CNOT Measured Network (CMN). The CMN uses only CNOT quantum gates and the measurement operator and as such is very simple to implement in any quantum computer technology. The CMN can by using only these two simple operators, result in a Turing universal operators AND and OR while keeping the learning speed optimized to the complex nature of the quantum network and a constant number of ancila qubits.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129536706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Amoeba-Inspired Electronic Solution-Searching System and Its Application to Finding Walking Maneuver of a Multi-legged Robot 受阿米巴启发的电子解搜索系统及其在多足机器人行走机动查找中的应用
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-07-19 DOI: 10.1109/ISMVL.2018.00030
Kenta Saito, Naoki Suefuji, S. Kasai, M. Aono
{"title":"Amoeba-Inspired Electronic Solution-Searching System and Its Application to Finding Walking Maneuver of a Multi-legged Robot","authors":"Kenta Saito, Naoki Suefuji, S. Kasai, M. Aono","doi":"10.1109/ISMVL.2018.00030","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00030","url":null,"abstract":"We have developed a bio-inspired electronic computing system, the \"electronic amoeba\". This system was designed to search for a solution to a combinational optimization problem, as inspired by foraging behavior of a single-celled amoeboid organism that is trying to maximize its food intake while satisfying given constraints. We electronically implement the system and demonstrate its solution search capability for solving the Boolean satisfiability problem, SAT. We apply the electronic amoeba to autonomous walking control of a multi-legged robot. Each leg joint has three-valued state and the electronic amoeba successively searches for a combination of the leg joint states to satisfy the objective of moving straight depending on the state of the robot.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116891820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Mining Latency Guarantees for RTL Designs RTL设计的挖掘延迟保证
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-16 DOI: 10.1109/ISMVL.2018.00020
Jan Malburg, Heinz Riener, G. Fey
{"title":"Mining Latency Guarantees for RTL Designs","authors":"Jan Malburg, Heinz Riener, G. Fey","doi":"10.1109/ISMVL.2018.00020","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00020","url":null,"abstract":"Guaranteed response times are crucial for control applications. Analyzing the communication latency, i.e., the time needed to transfer data from one end-point to another, in complex on-chip communication architectures is hard. In this paper, we formally define the problem of mining latency guarantees and present a pragmatic approach to mine symbolic conditions that guarantee a latency requirement. The verification problems handled in this approach are inherently multi-valued modeling bit-vectors of the underlying designs. We use the approach to infer the optimal transfer conditions for a bus bridge and an SPI-connection in less than a minute using only up to 5,000 clock cycles of simulation data.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123083924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Generation of Ternary Bent Functions by Spectral Invariant Operations in the Generalized Reed-Muller Domain 广义Reed-Muller域上谱不变运算生成三元弯曲函数
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-16 DOI: 10.1109/ISMVL.2018.00048
M. Stankovic, C. Moraga, R. Stankovic
{"title":"Generation of Ternary Bent Functions by Spectral Invariant Operations in the Generalized Reed-Muller Domain","authors":"M. Stankovic, C. Moraga, R. Stankovic","doi":"10.1109/ISMVL.2018.00048","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00048","url":null,"abstract":"Spectral invariant operations for ternary functions are defined as operations that preserve the absolute values of Vilenkin-Chrestenson spectral coefficients. Ternary bent functions are characterized as functions with a flat Vilenkin-Chrestenson spectrum, i.e., functions all whose spectral coefficients have the same absolute value. It follows that any function obtained by the application of one or more spectral invariant operations to a bent function will also be a bent function. This property is used in the present study to generate ternary bent functions efficiently in terms of space and time. For a software implementation of spectral invariant operations it is convenient to specify functions to be processed by the generalized Reed- Muller expressions. In this case, each invariant operation over a function f corresponds to adding one or more terms to the generalized Reed-Muller expression for f.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"227 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121040982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks 具有4 × 4交换块的可重构仲裁PUF
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-16 DOI: 10.1109/ISMVL.2018.00014
E. Dubrova
{"title":"A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks","authors":"E. Dubrova","doi":"10.1109/ISMVL.2018.00014","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00014","url":null,"abstract":"Physical Unclonable Functions (PUFs) exploit manufacturing process variation to create responses that are unique to individual integrated circuits (ICs). Typically responses of a PUF cannot be modified once the PUF is fabricated. In applications which use PUFs as a long-term secret key, it would be useful to have a simple mechanism for reconfiguring the PUF in order to update the key periodically. In this paper, we present a new type of arbiter PUFs which use 4 x 4 switch blocks instead of the conventional 2 x 2 ones. Each 4 x 4 switch block can be reconfigured in many different ways during the PUF's lifetime, making possible regular key updates.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An Analog-to-Digital Converter Using Delta-Sigma Modulator Network 基于Delta-Sigma调制器网络的模数转换器
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-16 DOI: 10.1109/ISMVL.2018.00013
T. Waho
{"title":"An Analog-to-Digital Converter Using Delta-Sigma Modulator Network","authors":"T. Waho","doi":"10.1109/ISMVL.2018.00013","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00013","url":null,"abstract":"An analog-to-digital converter (ADC) using a deltasigma modulator network is proposed, and signal-level simulations are carried out as a proof of concept. The present architecture is based on a feedforward artificial neural network, where an N-bit digital output is generated through N channels containing one comparator per channel. A moving average of delta-sigma modulator outputs is taken to obtain a multi-level feedforward signal. Simulation results show proper operations of present ADCs consisting of either first-order or second-order delta-sigma modulators. The effective number of bits (ENOB) increases as the number of channels increases. Comparison with conventional architectures is also discussed.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130469345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions 索引生成函数线性分解的zdd精确优化方法
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-16 DOI: 10.1109/ISMVL.2018.00033
Shinobu Nagayama, Tsutomu Sasao, J. T. Butler
{"title":"An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions","authors":"Shinobu Nagayama, Tsutomu Sasao, J. T. Butler","doi":"10.1109/ISMVL.2018.00033","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00033","url":null,"abstract":"This paper proposes an exact optimization method using zero-suppressed binary decision diagrams (ZDDs) for linear decomposition of index generation functions. The proposed method searches for an exact optimum solution by recursively dividing an index set of an index generation function. Since ZDDs can represent sets compactly and uniquely, they can also represent partitions of an index set compactly and uniquely. Thus, the proposed method can reuse partial solutions (partitions of an index set) efficiently by using ZDDs, and avoid redundant solution search. Experimental results using benchmark index generation functions show the effectiveness of ZDDs.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117211262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions 索引生成函数分解图的精确枚举方法
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2018-05-16 DOI: 10.1109/ISMVL.2018.00032
J. T. Butler, Tsutomu Sasao
{"title":"An Exact Method to Enumerate Decomposition Charts for Index Generation Functions","authors":"J. T. Butler, Tsutomu Sasao","doi":"10.1109/ISMVL.2018.00032","DOIUrl":"https://doi.org/10.1109/ISMVL.2018.00032","url":null,"abstract":"In a previous paper, the balls-in-bins model was shown to efficiently enumerate random functions as a means to estimate the size of programmable architecture for the circuit needed to realize an index generation function. Because there are so many balls-in-bins instances, it is typically not possible to enumerate all. So, a Monte Carlo simulation is performed instead. In this paper, we show how to improve the balls-in-bins estimates by using a weighted approach. An exact enumeration approach is also proposed that allows for the exhaustive enumeration of decomposition charts for the same analysis as in a previous paper. It is based on the enumeration of integer partitions.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129473726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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