Mining Latency Guarantees for RTL Designs

Guaranteed response times are crucial for control applications. Analyzing the communication latency, i.e., the time needed to transfer data from one end-point to another, in complex on-chip communication architectures is hard. In this paper, we formally define the problem of mining latency guarantees and present a pragmatic approach to mine symbolic conditions that guarantee a latency requirement. The verification problems handled in this approach are inherently multi-valued modeling bit-vectors of the underlying designs. We use the approach to infer the optimal transfer conditions for a bus bridge and an SPI-connection in less than a minute using only up to 5,000 clock cycles of simulation data.