一种节能的纳米电子学第四纪串行加法器

Shima Sedighiani, A. Kazemi
{"title":"一种节能的纳米电子学第四纪串行加法器","authors":"Shima Sedighiani, A. Kazemi","doi":"10.1109/ISMVL.2018.00016","DOIUrl":null,"url":null,"abstract":"Increased power consumption of scaling Complementary Metal Oxide Semiconductor (CMOS) technology and the limitations of binary communication have led to the consideration of non-silicon multiple-valued logic (MVL) circuits. The unique properties of Carbon Nanotube Field Effect Transistors (CNTFETs) in circuit design, such as the capability of setting the desired threshold voltage by adjusting the CNT diameters and the ballistic transport of carriers, make it possible to achieve an effective solution to improve energy efficiency and speed. Quaternary is the closest radix to the optimum (e=2.718) that has the advantage of easy communication with binary logic circuits. This study presents an efficient design of a quaternary serial adder based on CNTFETs. The design exploits an existing high-performance full adder and improves the carry propagation. Simulation results confirm that the proposed quaternary serial adder uses on average 57.8% of the power such an adder requires based on the current state-of-the-art quaternary full adders.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"An Energy-Efficient Quaternary Serial Adder for Nanoelectronics\",\"authors\":\"Shima Sedighiani, A. Kazemi\",\"doi\":\"10.1109/ISMVL.2018.00016\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Increased power consumption of scaling Complementary Metal Oxide Semiconductor (CMOS) technology and the limitations of binary communication have led to the consideration of non-silicon multiple-valued logic (MVL) circuits. The unique properties of Carbon Nanotube Field Effect Transistors (CNTFETs) in circuit design, such as the capability of setting the desired threshold voltage by adjusting the CNT diameters and the ballistic transport of carriers, make it possible to achieve an effective solution to improve energy efficiency and speed. Quaternary is the closest radix to the optimum (e=2.718) that has the advantage of easy communication with binary logic circuits. This study presents an efficient design of a quaternary serial adder based on CNTFETs. The design exploits an existing high-performance full adder and improves the carry propagation. Simulation results confirm that the proposed quaternary serial adder uses on average 57.8% of the power such an adder requires based on the current state-of-the-art quaternary full adders.\",\"PeriodicalId\":434323,\"journal\":{\"name\":\"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2018.00016\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2018.00016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

缩放互补金属氧化物半导体(CMOS)技术的功耗增加和二进制通信的局限性导致了对非硅多值逻辑(MVL)电路的考虑。碳纳米管场效应晶体管(cntfet)在电路设计中的独特特性,如通过调整碳纳米管直径和载流子的弹道输运来设置所需的阈值电压的能力,使其能够实现提高能效和速度的有效解决方案。四进制是最接近最优值(e=2.718)的基数,它具有易于与二进制逻辑电路通信的优点。本研究提出一种有效的四阶串联加法器的设计方法。该设计利用了现有的高性能全加法器,改进了进位传播。仿真结果证实,基于当前最先进的四元全加法器,所提出的四元串行加法器平均使用57.8%的功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Energy-Efficient Quaternary Serial Adder for Nanoelectronics
Increased power consumption of scaling Complementary Metal Oxide Semiconductor (CMOS) technology and the limitations of binary communication have led to the consideration of non-silicon multiple-valued logic (MVL) circuits. The unique properties of Carbon Nanotube Field Effect Transistors (CNTFETs) in circuit design, such as the capability of setting the desired threshold voltage by adjusting the CNT diameters and the ballistic transport of carriers, make it possible to achieve an effective solution to improve energy efficiency and speed. Quaternary is the closest radix to the optimum (e=2.718) that has the advantage of easy communication with binary logic circuits. This study presents an efficient design of a quaternary serial adder based on CNTFETs. The design exploits an existing high-performance full adder and improves the carry propagation. Simulation results confirm that the proposed quaternary serial adder uses on average 57.8% of the power such an adder requires based on the current state-of-the-art quaternary full adders.
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