{"title":"基于多电压/电流变换器的低功耗mtj真随机数发生器设计","authors":"Shogo Mukaida, N. Onizawa, T. Hanyu","doi":"10.1109/ISMVL.2018.00035","DOIUrl":null,"url":null,"abstract":"In this paper, we introduce a multi-V/I converter for low-power true random number generator (TRNG) using a three-terminal magnetic tunnel junction (MTJ) device. As MTJ devices are probabilistically switched by current, the desired probability of 50% is digitally controlled by digital-to-analog (D/A) and V/I converters. In the conventional MTJ-based TRNG a highly accurate (and large-power) D/A is required to be tolerate to large temperature variation of MTJ devices. By changing the characteristics dynamically according to the temperature variation, the proposed circuit can reduce the bit precision of the D/A converter while generating the quality of random number as the conventional V/I converter. The circuit is designed with a 65nm CMOS/three-terminal MTJ model, and the simulation is carried out using HSPICE. As a result, the number of bits of the D/A converter is reduced from 10 bits to 7 bits.","PeriodicalId":434323,"journal":{"name":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter\",\"authors\":\"Shogo Mukaida, N. Onizawa, T. Hanyu\",\"doi\":\"10.1109/ISMVL.2018.00035\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we introduce a multi-V/I converter for low-power true random number generator (TRNG) using a three-terminal magnetic tunnel junction (MTJ) device. As MTJ devices are probabilistically switched by current, the desired probability of 50% is digitally controlled by digital-to-analog (D/A) and V/I converters. In the conventional MTJ-based TRNG a highly accurate (and large-power) D/A is required to be tolerate to large temperature variation of MTJ devices. By changing the characteristics dynamically according to the temperature variation, the proposed circuit can reduce the bit precision of the D/A converter while generating the quality of random number as the conventional V/I converter. The circuit is designed with a 65nm CMOS/three-terminal MTJ model, and the simulation is carried out using HSPICE. As a result, the number of bits of the D/A converter is reduced from 10 bits to 7 bits.\",\"PeriodicalId\":434323,\"journal\":{\"name\":\"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2018.00035\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2018.00035","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter
In this paper, we introduce a multi-V/I converter for low-power true random number generator (TRNG) using a three-terminal magnetic tunnel junction (MTJ) device. As MTJ devices are probabilistically switched by current, the desired probability of 50% is digitally controlled by digital-to-analog (D/A) and V/I converters. In the conventional MTJ-based TRNG a highly accurate (and large-power) D/A is required to be tolerate to large temperature variation of MTJ devices. By changing the characteristics dynamically according to the temperature variation, the proposed circuit can reduce the bit precision of the D/A converter while generating the quality of random number as the conventional V/I converter. The circuit is designed with a 65nm CMOS/three-terminal MTJ model, and the simulation is carried out using HSPICE. As a result, the number of bits of the D/A converter is reduced from 10 bits to 7 bits.