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2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)最新文献

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Power Variance Analysis breaks a masked ASIC implementation of AES 功率方差分析打破了AES的掩码ASIC实现
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456966
Yang Li, K. Sakiyama, L. Batina, Daisuke Nakatsu, K. Ohta
{"title":"Power Variance Analysis breaks a masked ASIC implementation of AES","authors":"Yang Li, K. Sakiyama, L. Batina, Daisuke Nakatsu, K. Ohta","doi":"10.1109/DATE.2010.5456966","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456966","url":null,"abstract":"To obtain a better trade-off between cost and security, practical DPA countermeasures are not likely to deploy full masking that uses one distinct mask bit for each signal. A common approach is to use the same mask on several instances of an algorithm. This paper proposes a novel power analysis method called Power Variance Analysis (PVA) to reveal the danger of such implementations. PVA uses the fact that the side-channel leakage of parallel circuits has a big variance when they are given the same but random inputs. This paper introduces the basic principle of PVA and a series of PVA experiments including a successful PVA attack against a prototype RSL-AES implemented on SASEBO-R.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126374820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Feedback control for providing QoS in NoC based multicores 在基于NoC的多核中提供QoS的反馈控制
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457029
Akbar Sharifi, Hui Zhao, M. Kandemir
{"title":"Feedback control for providing QoS in NoC based multicores","authors":"Akbar Sharifi, Hui Zhao, M. Kandemir","doi":"10.1109/DATE.2010.5457029","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457029","url":null,"abstract":"In this paper, we employ formal feedback control theory to achieve desired communication throughput across a network-on-chip (NoC) based multicore. When the output of the system needs to follow a certain reference input over time, our controller regulates the system to obtain the desired effect on the output. In this work, targeting a multicore that executes multiple applications simultaneously, we demonstrate how to design and employ a PID (Proportional Integral Derivative) controller to obtain the desired throughput for communications by tuning the weights of the virtual channels of the routers in the NoC. We also propose a global controller architecture that implements policies to handle situations in which the network cannot provide the overlapping communications with sufficient resources or the throughputs of the communications can be enhanced (beyond their specified values) due to the availability of excess resources. Finally, we discuss how our novel control architecture works under different scenarios by presenting experimental results obtained using four embedded applications. These results show how the global controller adjusts the virtual channels weights to achieve the desired throughputs of different communications across the NoC, and as a result, the system output successfully tracks the specified input.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126587119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter 反射式脉搏血氧仪用于新生儿无创血氧饱和度监测
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457054
Wei Chen, Idowu Ayoola, Sidarto Bambang-Oetomo, L. Feijs
{"title":"Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter","authors":"Wei Chen, Idowu Ayoola, Sidarto Bambang-Oetomo, L. Feijs","doi":"10.1109/DATE.2010.5457054","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457054","url":null,"abstract":"Blood oxygen saturation is one of the key parameters for health monitoring of premature infants at the neonatal intensive care unit (NICU). In this paper, we propose and demonstrate a design of a wearable wireless blood saturation monitoring system. Reflectance pulse oxymeter based on Near Infrared Spectroscopy (NIRS) techniques are applied for enhancing the flexibility of measurements at different locations on the body of the neonates and the compatibility to be integrated into a non-invasive monitoring platform, such as a neonatal smart jacket. Prototypes with the reflectance sensors embedded in soft fabrics are built. The thickness of device is minimized to optimize comfort. To evaluate the performance of the prototype, experiments on the premature babies were carried out at NICU of Máxima Medical Centre (MMC) in Veldhoven, the Netherlands. The results show that the heart rate and SpO2 measured by the proposed design are corresponding to the readings of the standard monitor.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126742551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks KL-Cuts:一种针对多输出块的逻辑合成新方法
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456946
Osvaldo Martinello, F. Marques, R. Ribas, A. Reis
{"title":"KL-Cuts: A new approach for logic synthesis targeting multiple output blocks","authors":"Osvaldo Martinello, F. Marques, R. Ribas, A. Reis","doi":"10.1109/DATE.2010.5456946","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456946","url":null,"abstract":"This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the concept of factor cuts is extended to kl-cuts. Algorithms for computing this kind of cuts, including kl-cuts with unbounded k, are presented and results are shown. As a practical application, a covering algorithm using these cuts is presented.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127667200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Control network generator for latency insensitive designs 用于延迟不敏感设计的控制网络生成器
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457101
E. Kilada, K. Stevens
{"title":"Control network generator for latency insensitive designs","authors":"E. Kilada, K. Stevens","doi":"10.1109/DATE.2010.5457101","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457101","url":null,"abstract":"Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations have been suggested in the literature and each of these require a handshake control network (examples include synchronous elasticization and desynchronization). Numerous implementations of the control network are possible. This paper reports on an algorithm that has been proven to generate an optimal control network consisting of the minimum number of 2-input join and 2-output fork control components. This can substantially reduce the area and power consumption of a system. The algorithm has been implemented in a CAD tool, called CNG. It has been applied to the MiniMIPS processor showing a 14% reduction in the number of control steering units over a hand optimized design in a contemporary work.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113970978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analog circuit test based on a digital signature 基于数字签名的模拟电路测试
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457075
Alvaro Gómez, R. Sanahuja, L. Balado, J. Figueras
{"title":"Analog circuit test based on a digital signature","authors":"Alvaro Gómez, R. Sanahuja, L. Balado, J. Figueras","doi":"10.1109/DATE.2010.5457075","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457075","url":null,"abstract":"Production verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114347595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector 软输出ML - MIMO检测器的低复杂度高吞吐量VLSI架构
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457031
Teo Cupaiuolo, Massimiliano Siti, A. Tomasoni
{"title":"Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector","authors":"Teo Cupaiuolo, Massimiliano Siti, A. Tomasoni","doi":"10.1109/DATE.2010.5457031","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457031","url":null,"abstract":"In this paper a VLSI architecture of a high throughput and high performance soft-output (SO) MIMO detector (the recently presented Layered ORthogonal Lattice Detector, LORD) is presented. The baseline implementation includes optimal (i.e. maximum-likelihood - ML - in the max-log sense) SO generation. A reduced complexity variant of the SO generation stage is also described. To the best of the authors' knowledge, the proposed architecture is the first VLSI implementation of a max-log ML MIMO detector which includes QR decomposition and SO generation, having the latter a deterministic very high throughput thanks to a fully parallelizable structure, and parameterizability in terms of both the number of transmit and receive antennas, and the supported modulation orders. The two designs achieve a very high throughput making them particularly suitable for MIMO-OFDM systems like e.g. IEEE 802.11n WLANs: the most demanding requirements are satisfied at a reasonable cost of area and power consumption.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"104 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Toward optimized code generation through model-based optimization 通过基于模型的优化来优化代码生成
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457010
Asma Charfi, C. Mraidha, S. Gérard, F. Terrier, Pierre Boulet
{"title":"Toward optimized code generation through model-based optimization","authors":"Asma Charfi, C. Mraidha, S. Gérard, F. Terrier, Pierre Boulet","doi":"10.1109/DATE.2010.5457010","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457010","url":null,"abstract":"Model-Based Development (MBD) provides an additional level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic treatments of these models with dedicated tools like synthesis of system's application by automatic code generation. Real-Time and Embedded Systems (RTES) are often constrained by their environment and/or the resources they own in terms of memory, energy consumption with respect to performance requirements. Hence, an important problem to deal with in RTES development is linked to the optimization of their software part. Although automatic code generation and the use of optimizing compilers bring some answers to application optimization issue, we will show in this paper that optimization results may be enhanced by adding a new level of optimizations in the modeling process. Our arguments are illustrated with examples of the Unified Modeling Language (UML) state machines diagrams which are widely used for control aspect modeling of RTES. The well-known Gnu Compiler Collection (GCC) is used for this study. The paper concludes on a proposal of two step optimization approach that allows reusing as they are, existing compiler optimizations.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform 一种具有混合抽象级虚拟平台的精确系统架构精化方法
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457141
Zhe-Mao Hsu, J. Yeh, I-Yao Chuang
{"title":"An accurate system architecture refinement methodology with mixed abstraction-level virtual platform","authors":"Zhe-Mao Hsu, J. Yeh, I-Yao Chuang","doi":"10.1109/DATE.2010.5457141","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457141","url":null,"abstract":"The increasing complexity of today's system-on-a-chip (SoC) design is challenging the design engineers to evaluate the system performance and explore the design space. Electronic system-level (ESL) design methodology is of great help for attacking the challenges in recent years. In this paper, we present a system-level architecture refinement flow and implement a dual DSP cores virtual system based-on the highly accurate mixed abstraction-level modeling methodology. The constructed virtual platform can run various multimedia applications and achieve high accuracy. Compared with the traditional RTL simulation, the error rate is less than 5% and the simulation speed is around 100 times faster. Using the architecture refinement flow, the system performance profiling and architecture exploration is also realized for the software and hardware engineers to scrutinize the complicated system.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126162107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Scheduling for energy efficiency and fault tolerance in hard real-time systems 硬实时系统中能源效率和容错调度
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457039
Yu Liu, Han Liang, Kaijie Wu
{"title":"Scheduling for energy efficiency and fault tolerance in hard real-time systems","authors":"Yu Liu, Han Liang, Kaijie Wu","doi":"10.1109/DATE.2010.5457039","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457039","url":null,"abstract":"This paper studies the dilemma between fault tolerance and energy efficiency in frame-based real-time systems. Given a set of K tasks to be executed on a system that supports L voltage levels, the proposed heuristic-based scheduling technique minimizes the energy consumption of tasks execution when faults are absent, and preserves feasibility under the worst case of fault occurrences. The proposed technique first finds out the optimal solution in a comparable system that supports continuous voltage scaling, then converts the solution to the original system. The runtime complexity is only (LK2). Experimental results show that the proposed approach produces near-optimal results in polynomial time.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127523625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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