一种紧凑的90纳米CMOS数字调幅器

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI:10.1109/DATE.2010.5457112

V. Chironi, B. Debaillie, A. Baschirotto, J. Craninckx, M. Ingels

{"title":"一种紧凑的90纳米CMOS数字调幅器","authors":"V. Chironi, B. Debaillie, A. Baschirotto, J. Craninckx, M. Ingels","doi":"10.1109/DATE.2010.5457112","DOIUrl":null,"url":null,"abstract":"This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete−time to continuous−time conversion a 2−fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A compact digital amplitude modulator in 90nm CMOS\",\"authors\":\"V. Chironi, B. Debaillie, A. Baschirotto, J. Craninckx, M. Ingels\",\"doi\":\"10.1109/DATE.2010.5457112\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete−time to continuous−time conversion a 2−fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.\",\"PeriodicalId\":432902,\"journal\":{\"name\":\"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DATE.2010.5457112\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2010.5457112","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种用于极性发射机的90 nm CMOS数字调幅器。它采用2.45GHz的WLAN OFDM 64QAM调制，输出功率为- 2.5 dBmRMS, EVM为- 26.1 dB，效率为18%。为了减少由于离散时间到连续时间转换的别名，实现了2倍插值。该调幅器具有分段结构。这导致非常紧凑的0.007 mm2芯片面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A compact digital amplitude modulator in 90nm CMOS

This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete−time to continuous−time conversion a 2−fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

自引率

0.00%

发文量