V. Chironi, B. Debaillie, A. Baschirotto, J. Craninckx, M. Ingels
{"title":"A compact digital amplitude modulator in 90nm CMOS","authors":"V. Chironi, B. Debaillie, A. Baschirotto, J. Craninckx, M. Ingels","doi":"10.1109/DATE.2010.5457112","DOIUrl":null,"url":null,"abstract":"This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete−time to continuous−time conversion a 2−fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2010.5457112","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete−time to continuous−time conversion a 2−fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.