2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)最新文献_第10页

Multicore soft error rate stabilization using adaptive dual modular redundancy 基于自适应双模冗余的多核软误码率稳定

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457242

Ramakrishna Vadlamani, Jia Zhao, W. Burleson, R. Tessier

引用次数: 79

Digital statistical analysis using VHDL 数字统计分析使用VHDL

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456899

Manfred Dietrich, Uwe Eichler, J. Haase

引用次数: 2

Path-based scheduling in a hardware compiler 硬件编译器中基于路径的调度

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457011

Ruirui Gu, A. Forin, Richard Neil Pittman

引用次数: 1

Domain specific architecture for next generation wireless communication 下一代无线通信的领域特定架构

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457034

Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo, Ting Chen

引用次数: 9

An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability 一种用于汽车交流发电机的高压CMOS电压调节器，具有可编程功能和完全反极性能力

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457150

L. Fanucci, G. Pasetti, P. D'Abramo, R. Serventi, F. Tinfena, P. Chassard, L. Labiste, P. Tisserand

{"title":"An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability","authors":"L. Fanucci, G. Pasetti, P. D'Abramo, R. Serventi, F. Tinfena, P. Chassard, L. Labiste, P. Tisserand","doi":"10.1109/DATE.2010.5457150","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457150","url":null,"abstract":"This paper presents an innovative and effective approach to design and test a regulator for an automotive alternator with programmable functionalities. The prototype system consists of two different parts: an integrated circuit (IC) and a FPGA. The IC, implemented in austriamicrosystems HVCMOS 0.35 µm technology, includes all the high voltage parts and a power switch with very low ON resistance. It is able to manage full reverse polarity on every pin, including the reverse battery condition, and over voltages up to 50 V. The programmability is guaranteed through the FPGA. This prototype system can be used to develop a new type of intelligent smart and flexible regulators which implement many additional programmable functions that give the car maker a better control and allow to reduce vehicle fuel consumption and CO2 emissions. In the demonstrator all the implemented functions, including regulation, can be changed during the development phase and many properties, including loop stability, can be checked before releasing a final version of the regulator. The proposed system is also included in a standard brush-holder that can be mounted on Valeo Engine and Electrical System mechatronic alternator and verified directly in a real application.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114254344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A power optimization method for CMOS Op-Amps using sub-space based geometric programming 基于子空间几何规划的CMOS运放功率优化方法

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457151

Wei Gao, R. Hornsey

引用次数: 22

Energy-efficient real-time task scheduling with temperature-dependent leakage 具有温度相关泄漏的节能实时任务调度

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457243

Chuan-Yue Yang, Jian-Jia Chen, L. Thiele, Tei-Wei Kuo

{"title":"Energy-efficient real-time task scheduling with temperature-dependent leakage","authors":"Chuan-Yue Yang, Jian-Jia Chen, L. Thiele, Tei-Wei Kuo","doi":"10.1109/DATE.2010.5457243","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457243","url":null,"abstract":"Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different from many previous results, this paper explores leakageaware energy-efficient scheduling if leakage power consumption depends on temperature. We propose a pattern-based approach which divides a given time horizon into several time segments with the same length, where the processor is in the active (dormant, respectively) mode for a fixed amount of time at the beginning (end, respectively) of each time segment. Computation is advanced in the active mode, whereas the dormant mode helps reduce the temperature via cooling as well as the leakage power consumption. Since the pattern-based approach leads to a steady state with an equilibrium temperature, we develop a procedure to find the optimal pattern whose energy consumption in steady state is the minimum. Compared to existing work, our approach is more effective, has less run-time scheduling overhead, and requires only a simple scheduler to control the system mode periodically. The paper contains extensive simulation results which validate the new models and methods.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114086582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Skewed pipelining for parallel simulink simulations 用于并行simulink仿真的倾斜管道

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456927

A. Canedo, T. Yoshizawa, H. Komatsu

{"title":"Skewed pipelining for parallel simulink simulations","authors":"A. Canedo, T. Yoshizawa, H. Komatsu","doi":"10.1109/DATE.2010.5456927","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456927","url":null,"abstract":"Modern automotive and aerospace embedded applications require very high-performance simulations that are able to produce new values every microsecond. Simulations must now rely on scalable performance of multi-core systems rather than faster clock frequencies. Novel parallelization techniques are needed to satisfy the industrial simulation demands that are essential for the development of safety-critical systems. Simulink formalism is the industrial de facto standard, but current state-of-the-art simulation and code generation techniques fail to fully exploit the parallelism in modern multi-core systems. However, closed-loop and dynamic system simulations are very difficult to parallelize because of the loop-carried dependencies. In this paper we introduce a novel skewed pipelining technique that overcomes these difficulties and allows loop-carried Simulink applications to be executed concurrently in multi-core systems. By delaying the forwarding of values for a few iterations, we can break some data dependencies and coarsen the granularity of programs. This improves the concurrency and reduces the high cost of inter-processor communication. Implementation studies to demonstrate the viability of our method on a commodity multi-core system with 2, 3, and 4 processors show a 1.72, 2.38, and 3.33 fold speedup over uniprocessor execution.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114769037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Low power mobile internet devices using LTE technology 使用LTE技术的低功耗移动互联网设备

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456942

V. Aue

引用次数: 1

Post-placement temperature reduction techniques 放置后温度降低技术

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457127

Wei Liu, A. Nannarelli, A. Calimera, E. Macii, M. Poncino

引用次数: 3