2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)最新文献_第8页

Simultaneous budget and buffer size computation for throughput-constrained task graphs 同时预算和缓冲区大小计算的吞吐量约束任务图

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457082

M. Wiggers, M. Bekooij, M. Geilen, T. Basten

{"title":"Simultaneous budget and buffer size computation for throughput-constrained task graphs","authors":"M. Wiggers, M. Bekooij, M. Geilen, T. Basten","doi":"10.1109/DATE.2010.5457082","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457082","url":null,"abstract":"Modern embedded multimedia systems process multiple concurrent streams of data processing jobs. Streams often have throughput requirements. These jobs are implemented on a multiprocessor system as a task graph. Tasks communicate data over buffers, where tasks wait on sufficient space in output buffers before producing their data. For cost reasons, jobs share resources. Because jobs can share resources with other jobs that include tasks with date-dependent execution rates, we assume run-time scheduling on shared resources. Budget schedulers are applied, because they guarantee a minimum budget in a maximum replenishment interval. Both the buffer sizes as well as the budgets influence the temporal behaviour of a job. Interestingly, a trade-off exists: a larger buffer size can allow for a smaller budget while still meeting the throughput requirement. This work is the first to address the simultaneous computation of budget and buffer sizes.We solve this non-linear problem by formulating it as a second-order cone program. We present tight approximations to obtain a non-integral second-order cone program that has polynomial complexity. Our experiments confirm the non-linear trade-off between budget and buffer sizes.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An accurate system architecture refinement methodology with mixed abstraction-level virtual platform 一种具有混合抽象级虚拟平台的精确系统架构精化方法

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457141

Zhe-Mao Hsu, J. Yeh, I-Yao Chuang

引用次数: 15

Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks 利用非抢占调度任务的输出事件流之间的事件间流相关性

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457208

J. Rox, R. Ernst

引用次数: 22

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs 基于sram的fpga中多单元干扰的一种新的放置算法

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456995

L. Sterpone, N. Battezzati

{"title":"A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs","authors":"L. Sterpone, N. Battezzati","doi":"10.1109/DATE.2010.5456995","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456995","url":null,"abstract":"Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new FPGA devices very advantageous for space and avionics computing. However, larger levels of integration makes FPGA?'s configuration memory more prone to suffer Multi-Cell Upset errors (MCUs), caused by a single radiation particle that can flip the content of multiple nearby cells. In particular, MCUs are on the rise for the new generation of SRAM-based FPGAs, since their configuration memory is based on volatile programming cells designed with smaller geometries that result more sensitive to proton- and heavy ion-induced effects. MCUs drastically limits the capabilities of specific hardening techniques adopted in space-based electronic systems, mainly based on Triple Modular Redundancy (TMR). In this paper we describe a new placement algorithm for hardening TMR circuits mapped on SRAM-based FPGAs against the effects of MCUs. The algorithm is based on layout information of the FPGA?'s configuration memory and on metrics related to the logic and interconnection resources locations. Experimental results obtained from MCU static analysis on a set of benchmark circuits hardened by the proposed algorithm prove the efficiency of our approach.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128494416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Throughput modeling to evaluate process merging transformations in polyhedral process networks 多面体过程网络中评估过程合并转换的吞吐量建模

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456953

Sjoerd Meijer, Hristo Nikolov, T. Stefanov

引用次数: 32

A High-Voltage Low-Power DC-DC buck regulator for automotive applications 汽车用高压低功率DC-DC降压稳压器

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.5555/1870926.1871154

G. Pasetti, L. Fanucci, R. Serventi

引用次数: 10

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks KL-Cuts:一种针对多输出块的逻辑合成新方法

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456946

Osvaldo Martinello, F. Marques, R. Ribas, A. Reis

引用次数: 39

General behavioral thermal modeling and characterization for multi-core microprocessor design 多核微处理器设计的一般行为热建模和表征

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456979

T. Eguia, S. Tan, Ruijing Shen, E. H. Pacheco, M. Tirumala

{"title":"General behavioral thermal modeling and characterization for multi-core microprocessor design","authors":"T. Eguia, S. Tan, Ruijing Shen, E. H. Pacheco, M. Tirumala","doi":"10.1109/DATE.2010.5456979","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456979","url":null,"abstract":"This paper proposes a new architecture-level thermal modeling method to address the emerging thermal related analysis and optimization problem for high-performance multi-core microprocessor design. The new approach builds the thermal behavioral models from the measured or simulated thermal and power information at the architecture level for multi-core processors. Compared with existing behavioral thermal modeling algorithms, the proposed method can build the behavioral models from given arbitrary transient power and temperature waveforms used as the training data. Such an approach can make the modeling process much easier and less restrictive than before, and more amenable for practical measured data. The new method is based on a subspace identification method to build the thermal models, which first generates a Hankel matrix of Markov parameters, from which state matrices are obtained through minimum square optimization. To overcome the overfitting problems of the subspace method, the new method employs an overfitting mitigation technique to improve model accuracy and predictive ability. Experimental results on a real quad-core microprocessor show that ThermSID is more accurate than the existing ThermPOF method. Furthermore, the proposed overfitting mitigation technique is shown to significantly improve modeling accuracy and predictability.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Toward optimized code generation through model-based optimization 通过基于模型的优化来优化代码生成

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457010

Asma Charfi, C. Mraidha, S. Gérard, F. Terrier, Pierre Boulet

{"title":"Toward optimized code generation through model-based optimization","authors":"Asma Charfi, C. Mraidha, S. Gérard, F. Terrier, Pierre Boulet","doi":"10.1109/DATE.2010.5457010","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457010","url":null,"abstract":"Model-Based Development (MBD) provides an additional level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic treatments of these models with dedicated tools like synthesis of system's application by automatic code generation. Real-Time and Embedded Systems (RTES) are often constrained by their environment and/or the resources they own in terms of memory, energy consumption with respect to performance requirements. Hence, an important problem to deal with in RTES development is linked to the optimization of their software part. Although automatic code generation and the use of optimizing compilers bring some answers to application optimization issue, we will show in this paper that optimization results may be enhanced by adding a new level of optimizations in the modeling process. Our arguments are illustrated with examples of the Unified Modeling Language (UML) state machines diagrams which are widely used for control aspect modeling of RTES. The well-known Gnu Compiler Collection (GCC) is used for this study. The paper concludes on a proposal of two step optimization approach that allows reusing as they are, existing compiler optimizations.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Computation of yield-optimized Pareto fronts for analog integrated circuit specifications 模拟集成电路规范产量优化Pareto前沿的计算

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456971

Daniel Mueller-Gritschneder, H. Graeb

{"title":"Computation of yield-optimized Pareto fronts for analog integrated circuit specifications","authors":"Daniel Mueller-Gritschneder, H. Graeb","doi":"10.1109/DATE.2010.5456971","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456971","url":null,"abstract":"For any analog integrated circuit, a simultaneous analysis of the performance trade-offs and impact of variability can be conducted by computing the Pareto front of the realizable specifications. The resulting Specification Pareto front shows the most ambitious specification combinations for a given minimum parametric yield. Recent Pareto optimization approaches compute a so-called yield-aware specification Pareto front by applying a two-step approach. First, the Pareto front is calculated for nominal conditions. Then, a subsequent analysis of the impact of variability is conducted. In the first part of this work, it is shown that such a two-step approach fails to generate the most ambitious realizable specification bounds for mismatch-sensitive performances. In the second part of this work, a novel single-step approach to compute yield-optimized specification Pareto fronts is presented. Its optimization objectives are the realizable specification bounds themselves. Experimental results show that for mismatch-sensitive performances the resulting yield-optimized specification Pareto front is superior to the yieldaware specification Pareto front.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124018831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18