{"title":"RF design methodologies bridging system-IC-module design","authors":"R. Mullen","doi":"10.1109/ASPDAC.2004.1337625","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337625","url":null,"abstract":"There has been a long-standing need to link the RF design domains into a connected, common design environment. Such a methodology is possible through implementing system-level behavioral models with different levels of abstraction that can be modelled or co-simulated at the IC circuit level. At module or board design, it is possible to link and simulate multiple chips with board-level components and parastics in an RFIC design environment. With today's more complex IC designs that are heading toward nanometer-scaled semiconductor processes, there is a desire to further understand the many subtle physical IC characteristics, such as layout and substrate parasitics, RF transistor models, IR drops, electromigration, elctromagnetics, and modelling of on-chip spiral inductors. Designers have entered into an era where they could benefit from a balance between analog, digital, and DSP design all in a fast and automated RFIC design environment. We present RF design methodologies that can bridge between system, IC, and module design, providing an efficient, thorough design flow using advanced EDA tools.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132066649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, L. Karnan, S. Kita, K. Kotani, T. Ohmi
{"title":"The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration","authors":"T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, L. Karnan, S. Kita, K. Kotani, T. Ohmi","doi":"10.5555/1015090.1015237","DOIUrl":"https://doi.org/10.5555/1015090.1015237","url":null,"abstract":"A dynamically reeonfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developd. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit In order to accelerate emulation speed, a logic element, reducing total Configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support savdrestore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible processor.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qiming Zhu, H. Zhou, Tong Jing, Xianlong Hong, Yang Yang
{"title":"Efficient octilinear steiner tree construction based on spanning graphs","authors":"Qiming Zhu, H. Zhou, Tong Jing, Xianlong Hong, Yang Yang","doi":"10.1109/ASPDAC.2004.1337680","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337680","url":null,"abstract":"0ctilinear interconnect is a promising technique to shorten wire lengths. We present two practical heuristic octilinear Steiner tree (OSMT) algorithms in the paper. They are both based on octilinear spanning graphs. The one by edge substitution (OST-E) has a worst case running time of O(nlogn) and similar performance as the batched greedy algorithm[9]. The other one by triangle contraction (OST-T) has a small increase in running time and better performance. Experiments on both industry and random test cases are conducted.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131594737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Memory access driven storage assignment for variables in embedded system design","authors":"Yoonseo Choi, Taewhan Kim","doi":"10.1142/S0218126606003003","DOIUrl":"https://doi.org/10.1142/S0218126606003003","url":null,"abstract":"It has been reported and verified in many design experiences that a judicious utilization of the page/burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page/burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. To improve the quality of existing solutions, we propose a new storage assignment technique, called zone/spl I.bar/alignment, for variables, which effectively exploits an efficient 0-1 ILP formulation and the temporal locality of variables' accesses in code.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132619446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-level modeling of continuous-time /spl Delta//spl Sigma/ A/D-converters using formal models","authors":"E. Martens, G. Gielen","doi":"10.1109/ASPDAC.2004.1337539","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337539","url":null,"abstract":"Increasing complexity of modern mixed-signal chips requires systematic analysis and design methodologies. High-level formal models are a key ingredient for the high-level synthesis of systems-on-chip. We propose a formal description of continuous-time /spl Delta//spl Sigma/ modulators. The presented model makes it straightforward to analyze the converter at different levels of abstraction, including the major nonidealities. The model makes no assumptions about the topology, making it suited for the architectural exploration of /spl Delta//spl Sigma/ A/D-converters. A prototype has been implemented in the SystemC language showing the usefulness of the proposed model.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117117103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrating buffer planning with floorplanning for simultaneous multi-objective optimization","authors":"Yi-Hui Cheng, Yao-Wen Chang","doi":"10.1109/ASPDAC.2004.1337667","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337667","url":null,"abstract":"As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one of the most effective and popular techniques to reduce interconnnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert hundreds of thousands buffers during the post-layout starge when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floor-planning to ensure thiming closure and design convergence. In this paper, we drive the formulae of feasible regions, and integrate buffer planning with floor-planning to optimize area, timing, noise, and congestion (routability) simultaneously. In particular, we treat each buffer block as a soft module and apply Lagragian relaxation to optimize the floorplan area. Experimental results show that our method obtains an average suceess rate of 94.9% (86.4%) of nets meeting timimg constraint alone (both timing and noise constraints)and consumes an average extra area of only 0.1% (0.2%) over the given floorplan.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128308161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect capacitance estimation for FPGAs","authors":"J. Anderson, F. Najm","doi":"10.1109/ASPDAC.2004.1337686","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337686","url":null,"abstract":"The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and develop an empirical estimation model, suitable for use in power-aware placement, early power prediction, and other applications. We show that estimation accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also show that there is an inherent variability (noise) in the capacitance of nets routed using a commercial FPGA layout tool. This variability limits the accuracy attainable in capacitance estimation. Experimental results show that the proposed estimation model works well given the noise limitations.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129108477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ko Yoshikawa, Y. Hagihara, K. Kanamaru, Yuichi Nakamura, S. Inui, T. Yoshimura
{"title":"Timing optimization by replacing flip-flops to latches","authors":"Ko Yoshikawa, Y. Hagihara, K. Kanamaru, Yuichi Nakamura, S. Inui, T. Yoshimura","doi":"10.1109/ASPDAC.2004.1337563","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337563","url":null,"abstract":"Latch circuits have advantage for timing and are widely used for high-speed custom circuits. However, ASIC design flows are based on the circuits with flip-flops. Then, ASIC designers don't use latches. We describe a new timing optimization algorithm for ASIC by replacing flip-flops to latches without changing the functionality of the circuits. After latch replacement, restricted retiming called fixed-phase retiming is carried out for timing optimization by minimizing the impact of clock skew and jitter. The experimental results show that 17% delay improvement of the benchmark circuits is achieved by proposed algorithms.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127944539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine","authors":"Young-Il Kim, Bong-Il Park, Jae-Gon Lee, C. Kyung","doi":"10.1109/ASPDAC.2004.1337690","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337690","url":null,"abstract":"This paper describes an interface controller called SmartGlne which enables a pmcessor to interface with peripherals and makes a system reconfigurable by programming FPGA on the fly. By supporting standard interfaces and plug and play mechanism for the prncessor and FPGA, one can use any type of processors and FPGA¿s to implement a field programmable computing machine. The performance and utility of the SmartGlue was validated by applying its silicon implementation into a real system.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129286330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Combinatorial group testing methods for the BIST diagnosis problem","authors":"A. Kahng, S. Reda","doi":"10.1109/ASPDAC.2004.1337550","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337550","url":null,"abstract":"We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vectors, faulty scan cells, faulty modules, and faulty logic blocks in FPGAs. We develop an abstract model of this problem and show a fundamental correspondence to the well-established subject of combinatorial group testing (CGT) [Ding-Zhu Du et al., (1994)]. Armed with this new perspective, we show how to improve on a number of existing techniques in the VLSI diagnosis literature. In addition, we adapt and apply a number of CGT algorithms that are well-suited to the diagnosis problem in the digital realm. We also propose completely new methods and empirically evaluate the different algorithms. Our experiments show that results of the proposed algorithms outperform recent diagnosis techniques [J. Ghosh-Dastidar et al. (1999), (2000), J. Rajski et al. (1997)]. Finally, we point out future directions that can lead to new solutions for the BIST diagnosis problem.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128797994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}