High-level modeling of continuous-time /spl Delta//spl Sigma/ A/D-converters using formal models

Abstract

Increasing complexity of modern mixed-signal chips requires systematic analysis and design methodologies. High-level formal models are a key ingredient for the high-level synthesis of systems-on-chip. We propose a formal description of continuous-time /spl Delta//spl Sigma/ modulators. The presented model makes it straightforward to analyze the converter at different levels of abstraction, including the major nonidealities. The model makes no assumptions about the topology, making it suited for the architectural exploration of /spl Delta//spl Sigma/ A/D-converters. A prototype has been implemented in the SystemC language showing the usefulness of the proposed model.