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2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)最新文献

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Impact of chip and interposer PDN to eye diagram in high speed channels 芯片和中间体PDN对高速信道眼图的影响
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401673
F. de Paulis, Biyao Zhao, S. Piersanti, Jonghyun Cho, R. Cecchetti, B. Achkir, A. Orlandi, J. Fan
{"title":"Impact of chip and interposer PDN to eye diagram in high speed channels","authors":"F. de Paulis, Biyao Zhao, S. Piersanti, Jonghyun Cho, R. Cecchetti, B. Achkir, A. Orlandi, J. Fan","doi":"10.1109/SAPIW.2018.8401673","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401673","url":null,"abstract":"The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complete model of chip and interposer PDN is developed and, together to a lumped model of the PCB and package PDN, it is employed to supply I/O drivers for HBM traces laid out on silicon interposer. A comprehensive analysis is carried out highlighting the impact of the decoupling capacitor placement and their corresponding parasitic inductance on the supply voltage ripple and on the output eye diagram at the signal receivers.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123804270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Simulation of Nonuniform coupled transmission lines using approximated S-parameters model 用近似s参数模型模拟非均匀耦合传输线
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401652
A. Wardzinska, W. Bandurski
{"title":"Simulation of Nonuniform coupled transmission lines using approximated S-parameters model","authors":"A. Wardzinska, W. Bandurski","doi":"10.1109/SAPIW.2018.8401652","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401652","url":null,"abstract":"The paper presents the method of approximated S-Parameters calculation in application of Nonuniform Coupled Transmission Lines. In the work we present the network with two coupled tapered lines. The space dependence of RLC parameters of the lines are interpolated with analytical functions. The S parameters are calculated using the method of successive approximation. The output response to the trapezoidal input is presented and compared with the numerical solution of exact integral equations of the lines.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An on-chip load model for off-chip PDN analysis considering interdependency between supply voltage, current profile and clock latency 片外PDN分析的片上负载模型，考虑了电源电压、电流分布和时钟延迟之间的相互依赖性
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401655
Jun Chen, T. Kanamoto, H. Kando, M. Hashimoto
{"title":"An on-chip load model for off-chip PDN analysis considering interdependency between supply voltage, current profile and clock latency","authors":"Jun Chen, T. Kanamoto, H. Kando, M. Hashimoto","doi":"10.1109/SAPIW.2018.8401655","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401655","url":null,"abstract":"Simple yet accurate on-chip load model is demanded for off-chip power delivery network (PDN) design and verification. Conventionally, a current source that represents a short chip operation period is used for this purpose, but it cannot consider the interdependency between supply voltage, load current and clock latency. The ignorance of this interdependency could mislead off-chip PDN design causing over- and under-design. To address this issue, this paper proposes an on-chip load model with Verilog-A that can replay the load current and clock latency under dynamic supply noise. The model is expanded to support different chip operation modes, and it can be used as a sub-model to construct a large chip model. Experiment shows over 200X run-time improvement comparing with full SPICE netlist simulation. We also confirm that the current profile, power consumption, and clock latency are closely correlated.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impedance measurement in operating conditions for PLC applications PLC操作条件下的阻抗测量
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401649
O. Sabo, L. Pace, J. L. Le Bunetel, Anne-Sophie Descamps, C. Batard, N. Idir
{"title":"Impedance measurement in operating conditions for PLC applications","authors":"O. Sabo, L. Pace, J. L. Le Bunetel, Anne-Sophie Descamps, C. Batard, N. Idir","doi":"10.1109/SAPIW.2018.8401649","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401649","url":null,"abstract":"The influence of the electromagnetic environment of the indoor power line grid (Houses' Power Grid) is increasingly important on the Power Line Communication transmission. The household equipment operating changes considerably the network impedance. Several procedures exist to evaluate the network impedance. Two impedance measurement techniques seem to be the most adequate and allow to characterize loads under their operating conditions. The first one uses current injection and reception probes and the second one uses capacitive coupling. With a proper pre-measurement calibration process, the proposed methods allow to measure the evolution of the impedance versus frequency of the active loads (TV screen, Fluorescent lamp…). This study deals with the analyses of these two methods in order to evaluate their advantages and disadvantages. The measurements are carried in narrowband and broadband in the frequency range of 10 kHz to 100 MHz.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125357172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation and comparison of mounted inductance for decoupling capacitor 去耦电容安装电感的评估与比较
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401647
Benoît Goral, C. Gautier, A. Amédéo
{"title":"Evaluation and comparison of mounted inductance for decoupling capacitor","authors":"Benoît Goral, C. Gautier, A. Amédéo","doi":"10.1109/SAPIW.2018.8401647","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401647","url":null,"abstract":"In this article, different patterns for decoupling capacitor routed on a dedicated test vehicle are compared. The aim of this study is, on one hand to confirm design rules for enhanced decoupling on printed circuit board and on the other hand, to estimate the value of the mounted inductance introduced by each pattern. Each mounting pattern and the particular parameter which is studied for each case will be described and measurement methodology as mounted inductance calculation will be presented. Then, mounted inductance calculated from measurement and results given by simulation are compared in order to see the precision reached by recent hybrid EM solver dedicated to Printed Circuit Board for parasitic elements calculation. Finally design rules and trade off for better decoupling are given as a conclusion.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124604268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DDR5 design challenges DDR5设计挑战
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401666
B. Nitin, W. Randy, Ikeda Shinichiro, Fujine Eiji, Ryouichi Shibata, Sugaya Yumiko, Ono Megumi
{"title":"DDR5 design challenges","authors":"B. Nitin, W. Randy, Ikeda Shinichiro, Fujine Eiji, Ryouichi Shibata, Sugaya Yumiko, Ono Megumi","doi":"10.1109/SAPIW.2018.8401666","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401666","url":null,"abstract":"Operating a DDR4 memory channel at speeds of only 2666MT/s can be a challenge for multi-slot setups. So what will be required in the next-generation DDR5 memory busses to enable them to run at speeds of 3200MT/s and above? What are the implications for controllers, and how does one plan the supported topologies for a given controller?","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131774195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Eye diagram estimation and equalizer design method for PAM4 PAM4眼图估计及均衡器设计方法
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401645
Wei-Ju Chang, R. Wu
{"title":"Eye diagram estimation and equalizer design method for PAM4","authors":"Wei-Ju Chang, R. Wu","doi":"10.1109/SAPIW.2018.8401645","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401645","url":null,"abstract":"The extended peak distortion analysis (ePDA) is proposed in this paper for the eye diagram estimation of high speed interconnects in PAM4. The method can construct the eye diagram much faster than by PRBS eye simulation. In addition, the genetic algorithm is established to find the optimal tap numbers and coefficients of the feed-forward equalizer (FFE) so as to minimize the inter-symbol interference (ISI) effectively and efficiently.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116913407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fully 3-D BIE evaluation of the resistance and inductance of on-board and on-chip interconnects 对板上和片上互连的电阻和电感进行了全三维BIE评估
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401653
Martijn Huynen, D. De Zutter, D. Ginste
{"title":"A fully 3-D BIE evaluation of the resistance and inductance of on-board and on-chip interconnects","authors":"Martijn Huynen, D. De Zutter, D. Ginste","doi":"10.1109/SAPIW.2018.8401653","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401653","url":null,"abstract":"In this contribution, the resistance and inductance of 3-D interconnects are obtained through a full-wave approach. By solving a free space boundary integral equation (BIE) combined with a fully 3-D differential surface admittance operator in a circuit framework, an effective procedure to study finite conductivity interconnects is presented. The accuracy of the proposed method in characterizing 3-D interconnects is demonstrated through an on-board and an on-chip example.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124564650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Impact of the doped areas sizes in the performances of microwave SPST switches integrated in a silicon substrate 掺杂面积大小对集成在硅衬底中的微波SPST开关性能的影响
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401644
R. Allanic, D. Le Berre, Y. Quéré, C. Quendo, D. Chouteau, V. Grimal, D. Valente, J. Billoué
{"title":"Impact of the doped areas sizes in the performances of microwave SPST switches integrated in a silicon substrate","authors":"R. Allanic, D. Le Berre, Y. Quéré, C. Quendo, D. Chouteau, V. Grimal, D. Valente, J. Billoué","doi":"10.1109/SAPIW.2018.8401644","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401644","url":null,"abstract":"This paper deals with the impact of the doped areas sizes on the performances of microwave switches. The RF switches are designed on a silicon substrate in microstrip technology and use semiconductors diodes (N+P junctions) as active elements to commute from the OFF-state to the ON-state. Therefore, the co-design of the microstrip transmission lines and the active elements gives a great design flexibility. The manufacturing process is based on classical steps used to fabricate semiconductor components and this allows to choose the size of the active elements (i.e. the size of the doped areas). Five demonstrators with as many different integrated diode sizes are presented and the size impact on their performances is discussed on the frequency band going from 0.1 GHz to 10 GHz. With a very low bias voltage, the insertion losses are lower than 2 dB and the isolation can be higher than 40 dB.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127549550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Powering a remote board and sensors in an extreme environment — An optical solution 在极端环境下为远程板和传感器供电-一种光学解决方案
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI) Pub Date : 2018-05-22 DOI: 10.1109/SAPIW.2018.8401646
C. Diouf, L. Ghisa, Ramez Hamié, V. Quintard, M. Guegan, A. Pérennou, Laurent Gautier, M. Tardivel, Stéphane Barbot, F. Colas
{"title":"Powering a remote board and sensors in an extreme environment — An optical solution","authors":"C. Diouf, L. Ghisa, Ramez Hamié, V. Quintard, M. Guegan, A. Pérennou, Laurent Gautier, M. Tardivel, Stéphane Barbot, F. Colas","doi":"10.1109/SAPIW.2018.8401646","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401646","url":null,"abstract":"This short paper is an advanced proof-of-concept of an optically powered board designed for seabed monitoring operations. The application features a very particular case of interference between data signals and power supply. The paper mainly focuses on measurements based on a recent prototype that validate previous results mostly obtained by simulation.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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