B. Nitin, W. Randy, Ikeda Shinichiro, Fujine Eiji, Ryouichi Shibata, Sugaya Yumiko, Ono Megumi
{"title":"DDR5设计挑战","authors":"B. Nitin, W. Randy, Ikeda Shinichiro, Fujine Eiji, Ryouichi Shibata, Sugaya Yumiko, Ono Megumi","doi":"10.1109/SAPIW.2018.8401666","DOIUrl":null,"url":null,"abstract":"Operating a DDR4 memory channel at speeds of only 2666MT/s can be a challenge for multi-slot setups. So what will be required in the next-generation DDR5 memory busses to enable them to run at speeds of 3200MT/s and above? What are the implications for controllers, and how does one plan the supported topologies for a given controller?","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"DDR5 design challenges\",\"authors\":\"B. Nitin, W. Randy, Ikeda Shinichiro, Fujine Eiji, Ryouichi Shibata, Sugaya Yumiko, Ono Megumi\",\"doi\":\"10.1109/SAPIW.2018.8401666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Operating a DDR4 memory channel at speeds of only 2666MT/s can be a challenge for multi-slot setups. So what will be required in the next-generation DDR5 memory busses to enable them to run at speeds of 3200MT/s and above? What are the implications for controllers, and how does one plan the supported topologies for a given controller?\",\"PeriodicalId\":423850,\"journal\":{\"name\":\"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SAPIW.2018.8401666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAPIW.2018.8401666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Operating a DDR4 memory channel at speeds of only 2666MT/s can be a challenge for multi-slot setups. So what will be required in the next-generation DDR5 memory busses to enable them to run at speeds of 3200MT/s and above? What are the implications for controllers, and how does one plan the supported topologies for a given controller?
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