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2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A Compact CMOS 76–82 GHz Super-Harmonic VCO with 189 dBc/Hz FoM Operating based on Harmonic-Assisted ISF Manipulation 一种基于谐波辅助ISF操作的189dbc /Hz FoM超谐波压控振荡器
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863140
Behnam Moradi, Xuyang Liu, Michael M. Green, Hamidreza Aghasi
{"title":"A Compact CMOS 76–82 GHz Super-Harmonic VCO with 189 dBc/Hz FoM Operating based on Harmonic-Assisted ISF Manipulation","authors":"Behnam Moradi, Xuyang Liu, Michael M. Green, Hamidreza Aghasi","doi":"10.1109/RFIC54546.2022.9863140","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863140","url":null,"abstract":"A compact super- harmonic voltage-controlled oscillator (VCO) for mm-wave radar applications employing a novel distributed structure operating at a center frequency of 78.9 GHz is presented. An state-of-the-art phase-noise performance is achieved by leveraging the strong presence of second harmonic at the output. This new VCO structure operates based on the minimization of the thermal noise contribution for fundamental signal and thus, improves the phase noise. The V CO is fabricated in 65nm Bulk CMOS technology and attains a measured phase-noise of −109.82 dBc/Hz at 1 MHz offset frequency, corresponding to a figure-of-merit of 189dBc/Hz. The VCO also demonstrates 7 % of frequency tuning, 4.6 % efficiency, and −0.6 dBm peak output power. To the best of our knowledge, this is the highest reported FOM for a super-harmonic CMOS oscillator operating at this frequency band.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121392369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2MHz 4-48V $mathrm{V}_{text{IN}}$ Flying-Capacitor Based Floating-Ground GaN DC-DC Converter with Real-Time Inductor Peak-Current Detection and $6mu mathrm{s}$ Load Transient Response 一种2MHz 4-48V $ mathm {V}_{text{IN}}$基于飞电容的浮地GaN DC-DC变换器，具有实时电感峰值电流检测和$6 mathm {s}$负载瞬态响应
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863089
Weizhong Chen, Chang Yang, Lei Chen, P. Gui
{"title":"A 2MHz 4-48V $mathrm{V}_{text{IN}}$ Flying-Capacitor Based Floating-Ground GaN DC-DC Converter with Real-Time Inductor Peak-Current Detection and $6mu mathrm{s}$ Load Transient Response","authors":"Weizhong Chen, Chang Yang, Lei Chen, P. Gui","doi":"10.1109/RFIC54546.2022.9863089","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863089","url":null,"abstract":"This paper presents a 2MHz 4V-to-48V VIN, GaN-based buck-boost converter with optimized buck-boost mode, enhanced safe protection, and fast transient response for automotive Advanced Driving Assistant Systems (ADAS). A flying-capacitor-based floating-ground topology is proposed first time to solve the issue associated with extremely short on time, improve power efficiency in the buck-boost region and provide real-time detection and management of the inductor peak current. This floating-ground technique helps alleviate the problem of efficiency drop in the four-switch buck-boost topology and ensures converter/load safety. An indirect current sensor is also proposed, which allows for sensing the inductor current change in the buck-boost mode without using any bulky sensing resistors and achieves $k$ fast transient response with 100mv-undershoot/80mV-overshoot for 1A load current change. This converter achieves a maximum efficiency of 92% which is comparable to the state-of-the-art buck-boost schemes","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-beam, Scalable 28 GHz Relay Array with Frequency and Spatial Division Multiple Access Using Passive, High-Order N-Path Filters 多波束，可扩展的28ghz中继阵列，使用无源高阶n路滤波器进行频率和空域多址访问
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863113
P. Khial, Samir Nooshabadi, Austin C. Fikes, A. Hajimiri
{"title":"Multi-beam, Scalable 28 GHz Relay Array with Frequency and Spatial Division Multiple Access Using Passive, High-Order N-Path Filters","authors":"P. Khial, Samir Nooshabadi, Austin C. Fikes, A. Hajimiri","doi":"10.1109/RFIC54546.2022.9863113","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863113","url":null,"abstract":"A 28 GHz scalable relay array that independently re-routes multiple beamformed data-channels in different frequency bands is presented, allowing for frequency and spatial division multiple access. The array is implemented at the element-level with a 65 nm CMOS RFIC that has two transmit-and-receive branches. Each transmit-and-receive branch provides phase delay, true time delay, and amplitude control for up to 3 frequency channels independently and simultaneously. The baseband signal chain is enabled by a dual function N-path filter architecture that is passive and inductorless yet provides high-order filtering with complex roll-off and performs phase shifting. The resulting array consists of a 2-chip, 4-branch prototype that independently steers 3 frequency multiplexed incident data beams into different spatial directions, with true time delay control in each beam. A radiative measurement shows the router supporting a simultaneous throughput of 625 Mb/s 32-QAM data across 3 frequency channels that are independently spatially steered.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and −250.3dB FoM 一种21.8-41.6GHz带死区自动控制器的快速锁定子采样锁相环，实现62.7 fs抖动和- 250.3dB FoM
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863104
Wen Chen, Yiyang Shu, H. Qian, J. Yin, Pui-in Mak, Xiang Gao, Xun Luo
{"title":"A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and −250.3dB FoM","authors":"Wen Chen, Yiyang Shu, H. Qian, J. Yin, Pui-in Mak, Xiang Gao, Xun Luo","doi":"10.1109/RFIC54546.2022.9863104","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863104","url":null,"abstract":"In this paper, a wideband fast-locking millimeter-wave (mmW) sub-sampling PLL (SSPLL) with low jitter is proposed. A quadrature sub-sampling phase detector (QSSPD)-based dead zone automatic controller (DZAC) is introduced to automatically switch on the frequency-locked loop (FLL) for fast-locking. Here, the long locking time caused by the dead zone of FLL is eliminated. The mmW quad-mode oscillator is integrated in the SSPLL to achieve the low jitter within a wide frequency range. The proposed SSPLL is fabricated in a 40-nm CMOS technology. Measurements exhibit a frequency tuning range of 62.5% from 21.8 to 41.6GHz. The SSPLL achieves a 62.7 to 79.1fs rms jitter within the frequency tuning range. Besides, the typical power consumption is 23.6mW, leading to a PLL FoM of −248.3 to −250.3dB. Meanwhile, the proposed SSPLL achieves more than $8.9times$ locking time improvement. The PLL occupies a core area of $0.18text{mm}^{2}$.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128883305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 23 G Hz RF - beamforming Transmitter with > 15.5 dBm $mathrm{P}_{text{sat}}$ and >21.7% Peak Efficiency for Inter-satellite Communications 一种23g Hz射频波束形成发射机，具有> 15.5 dBm $ mathm {P}_{text{sat}}$和>21.7%的星间通信峰值效率
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863123
Kaijie Ding, D. Milosevic, V. Vidojkovic, Rainier van Dommele, M. Bentum, P. Baltus
{"title":"A 23 G Hz RF - beamforming Transmitter with > 15.5 dBm $mathrm{P}_{text{sat}}$ and >21.7% Peak Efficiency for Inter-satellite Communications","authors":"Kaijie Ding, D. Milosevic, V. Vidojkovic, Rainier van Dommele, M. Bentum, P. Baltus","doi":"10.1109/RFIC54546.2022.9863123","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863123","url":null,"abstract":"This paper presents a 23GHz RF -beamforming transmitter (TX) for inter-satellite communications. By combining a variable gain amplifier (VGA), a phase shifter (PS), and a four-inductor-coupling differential quadrature-signal (IQ) generator, a power-efficient design with high compactness is demonstrated. The chip is fabricated in a 130nm SiGe BiCMOS technology. It achieves a measured saturated output power (Psat) of >15.5dBm and a peak TX efficiency of >21.7%, with 2.09° RMS phase error and >29.3dB maximum power gain. The realized mm-wave TX supports 64-QAM with a 900Mbps data rate, the Error Vector Magnitude (EVM) of 4.98% (-26.06dB), the Adjacent Channel Power Ratio (ACPR) of −30.1dBc, and TX efficiency of 8.52% are measured at 9.2dBm output power. The core area of this TX is 0.9mm x 0.23mm.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121977947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 14.5-17.9 GHz Harmonically-Coupled Quad-Core P-N Class-B DCO with -117.3 dBc/Hz Phase Noise at 1 MHz Offset in 28-nm CMOS 一种14.5-17.9 GHz四核P-N b类DCO，在1mhz偏移时相位噪声为-117.3 dBc/Hz
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863180
Ioanna Apostolina, D. Manstretta
{"title":"A 14.5-17.9 GHz Harmonically-Coupled Quad-Core P-N Class-B DCO with -117.3 dBc/Hz Phase Noise at 1 MHz Offset in 28-nm CMOS","authors":"Ioanna Apostolina, D. Manstretta","doi":"10.1109/RFIC54546.2022.9863180","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863180","url":null,"abstract":"In this paper, a CMOS quad-core DCO with class-B operation and transformer-based tail coupling is investigated to achieve ultra-low phase noise in the Ku band. The design uses an averaging approach to minimize systematic frequency step errors arising in DCOs with large tuning capacitor arrays due to signal unequal distribution. A proof-of-concept prototype has been developed in 28-nm CMOS technology. The DCO achieves a phase noise of−117.3 dBc/Hz at 1 MHz offset from the 15.35 GHz carrier frequency, a figure of merit (FoM) of -187.6 dBc/Hz, and a tuning range of 20.3% with a frequency resolution of 10MHz and less than ±240 kHz error.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125991749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
2022 IEEE RFIC Symposium 2022年IEEE RFIC研讨会
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/rfic54546.2022.9863199
{"title":"2022 IEEE RFIC Symposium","authors":"","doi":"10.1109/rfic54546.2022.9863199","DOIUrl":"https://doi.org/10.1109/rfic54546.2022.9863199","url":null,"abstract":"","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Superior Reliability and Low Self-Heating of a 45nm CMOS 39-GHz Power Amplifier for 5G mmWave Applications 用于5G毫米波应用的45nm CMOS 39-GHz功率放大器的高可靠性和低自热
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863154
P. Srinivasan, S. Syed, J. A. Sundaram, S. Moss, S. Jain, P. Colestock, N. Cahoon, A. Bandyopadhyay, F. Guarín, B. Min, M. Gall
{"title":"Superior Reliability and Low Self-Heating of a 45nm CMOS 39-GHz Power Amplifier for 5G mmWave Applications","authors":"P. Srinivasan, S. Syed, J. A. Sundaram, S. Moss, S. Jain, P. Colestock, N. Cahoon, A. Bandyopadhyay, F. Guarín, B. Min, M. Gall","doi":"10.1109/RFIC54546.2022.9863154","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863154","url":null,"abstract":"A 5G new-radio (NR) 2-stack differential 39 GHz Power Amplifier (P A) designed with ADNFETs in 45RFSOI technology is used to showcase superior CW and 5G performance and excellent reliability. Measured CW linear gain of ~12 dB, ~18 dBm Psat with P AE of 35.1 % is seen while 5G QPSK results show Plin ~13dBm@-22dB EVM and ~17dBm@-19dB ACPR at 1.7V VDD back-off conditions. Time domain waveforms followed by RF reliability characterization show that off-state Hot Carrier Injection (HCI) is a key fail mechanism under matched-Z load and VSWR. Key RF degradation metrics from long term RF stress show $Delta mathbf{Pout}, Delta mathbf{Gain} < 0.5mathbf{dBm}$ and $Delta mathbf{PAR} < 1%$ meeting overall 10yr lifetime criteria. Self-heating characterization show ~6 C increase at 1.6V/160mW dissipated power demonstrating excellent thermal stability. From 5G aging measurements and model sims, good model-hardware correlation is seen where gain degradation < 0.5 dB at 10y demonstrating overall superior performance and excellent reliability of the P A for 5G mm Wave applications.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Millimeter-Wave Front-End for FD/FDD Transceivers Featuring an Embedded PA and an N-Path Filter Based Circulator Receiver 一种用于FD/FDD收发器的毫米波前端，具有嵌入式PA和基于n路滤波器的环形接收器
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863209
Masoud Pashaeifar, L. D. de Vreede, M. Alavi
{"title":"A Millimeter-Wave Front-End for FD/FDD Transceivers Featuring an Embedded PA and an N-Path Filter Based Circulator Receiver","authors":"Masoud Pashaeifar, L. D. de Vreede, M. Alavi","doi":"10.1109/RFIC54546.2022.9863209","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863209","url":null,"abstract":"This work presents an ultra-compact single-antenna FD/FDD transceivers front-end. It comprises a nonreciprocal circulator, RX, and an integrated power amplifier (PA). In the proposed circulator, we devise a ring quarter-wave transmission line topology with adjusted characteristic impedances to improve TX-to-antenna insertion loss and TX-to-RX isolation. Besides, an AND-gate switching-based N-path filter is proposed to realize the circulator's nonreciprocal gyrator while acting as a mixer-first RX. Owing to the ultra-compact N-path filter structure, the circulator occupies only 0.38mm2 core area. Over a 27.1-to-31.1GHz band, the realized front-end offers >20dB TX-to-RX isolation while its measured TX-to-antenna insertion loss is 1.7~2.2dB. The RX path tolerates the PA's blocker signal, achieving 5dBm in-band and 13dBm out-of-band B1dB.Moreover, the PA delivers 15.15dBm peak output power with 33% drain efficiency. Our front-end prototype occupies only 0.7mm2, including circulator, PA, quadrature hybrid coupler LO generators, and baseband circuits.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129116012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
22–33 GHz CMOS LNA Using Coupled-TL Feedback and Body Self-Forward-Bias for 28 GHz 5G System 采用耦合tl反馈和本体自正向偏置的22-33 GHz CMOS LNA用于28 GHz 5G系统
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863213
Yo‐Sheng Lin, K. Lan
{"title":"22–33 GHz CMOS LNA Using Coupled-TL Feedback and Body Self-Forward-Bias for 28 GHz 5G System","authors":"Yo‐Sheng Lin, K. Lan","doi":"10.1109/RFIC54546.2022.9863213","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863213","url":null,"abstract":"We report a 22–33 GHz low-noise amplifier (LNA) with low power dissipation (PD), low noise-figure (NF) and small group-delay (GD) variation in 90 nm CMOS for 28 GHz 5G system. Current-reused and body self-forward-bias (BSFB) techniques are used for low PD. Compact quarter-wavelength (λ/4) spiral transmission-line (TL) in conjunction with a large bypass capacitor is used for gate-bias and simultaneous drain-bias and current-source. Coupled-TL feedback and BSFB techniques are used for gain and NF enhancement in the condition of the same PD. The LNA dissipates 12.2 mW and achieves decent S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22–33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB and GD variation of ±6 ps for 22–33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Furthermore, the LNA occupies 0.406 mm2 chip area, and attains decent input third-order intercept point (IIP3) of -3 dBm at 28 GHz. The NF and FOM are one of the best performances ever demonstrated for Ka-band CMOS LNAs with f3dB wider than 5 GHz and PD lower than 14 mW.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117266962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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