{"title":"A Compact Single Transformer Footprint Hybrid Current-Voltage Digital Doherty Power Amplifier","authors":"Jeongseok Lee, Doohwan Jung, D. Munzer, Hua Wang","doi":"10.1109/RFIC54546.2022.9863084","DOIUrl":null,"url":null,"abstract":"This paper presents a fully integrated single footprint hybrid current-voltage mode digital Doherty power amplifier (PA). A prototype PA is implemented in a 45nm CMOS SOI process. The proposed PA design provides enhanced linearity through adaptive biasing-based AM-PM distortion mitigation of the current mode digital PA and AM-PM cancelation through hybrid current/voltage mode Doherty-based power combining. It achieves 21.7dBm peak output power $(\\mathrm{P}_{\\text{sat}})$ at 1.2GHz and 37.6% drain efficiency (DE) at 1.4GHz. The proposed digital Doherty PA demonstrates $1.2\\times/1.22\\times \\text{PBO}$ efficiency enhancement, compared to the ideal class-B at 3/6 dB PBO at 1.2GHz. The measured error vector magnitude (EVM) of 64-QAM/20MHz is −23dB with 22.8% average DE without DPD. This is the first demonstration of hybrid current-voltage mode Doherty power combining on a single footprint transformer over a broad bandwidth (BW)","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"9 11","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863084","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a fully integrated single footprint hybrid current-voltage mode digital Doherty power amplifier (PA). A prototype PA is implemented in a 45nm CMOS SOI process. The proposed PA design provides enhanced linearity through adaptive biasing-based AM-PM distortion mitigation of the current mode digital PA and AM-PM cancelation through hybrid current/voltage mode Doherty-based power combining. It achieves 21.7dBm peak output power $(\mathrm{P}_{\text{sat}})$ at 1.2GHz and 37.6% drain efficiency (DE) at 1.4GHz. The proposed digital Doherty PA demonstrates $1.2\times/1.22\times \text{PBO}$ efficiency enhancement, compared to the ideal class-B at 3/6 dB PBO at 1.2GHz. The measured error vector magnitude (EVM) of 64-QAM/20MHz is −23dB with 22.8% average DE without DPD. This is the first demonstration of hybrid current-voltage mode Doherty power combining on a single footprint transformer over a broad bandwidth (BW)