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A 16 kV PV Inverter Using Series-Connected 10 kV SiC MOSFET Devices 一种采用串联10kv SiC MOSFET器件的16kv光伏逆变器
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372078
R. Burgos, D. Dong, X. Lin, L. Ravi
{"title":"A 16 kV PV Inverter Using Series-Connected 10 kV SiC MOSFET Devices","authors":"R. Burgos, D. Dong, X. Lin, L. Ravi","doi":"10.1109/IEDM13553.2020.9372078","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372078","url":null,"abstract":"This paper presents the design, construction and testing of a photovoltaic (PV) three-phase inverter capable of direct-to-line (transformer-less) operation, rated for 200 W, 11 kV ac, and 16 kV dc, featuring a simple two-level inverter topology using series-connected 10 kV Silicon-Carbide (SiC) MOSFET de-vices operating as an equivalent ‘20 kV switch,’ and using printed-circuit-board (PCB) based ac and dc distributed capacitor arrays to achieve zero-partial-discharge operation. Experimental results demonstrate the excellent performance achieved, including an efficiency of 99 % and a specific power of 5 kW/kg.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121173364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process 具有回流功能的嵌入式8Mb STT-MRAM宏，在16nm FinFET逻辑CMOS工艺中具有9nS读访问时间
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372115
Y. Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Ku-Feng Lin, T. Chiang, Yuan-Jen Lee, K. Shen, Roger Wang, Wayne Wang, H. Chuang, Eric Wang, Y. Chih, Jonathan Chang
{"title":"A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process","authors":"Y. Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Ku-Feng Lin, T. Chiang, Yuan-Jen Lee, K. Shen, Roger Wang, Wayne Wang, H. Chuang, Eric Wang, Y. Chih, Jonathan Chang","doi":"10.1109/IEDM13553.2020.9372115","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372115","url":null,"abstract":"In this paper, we present the design and silicon characterization results of an 8Mb STT-MRAM macro in 16nm FinFET Logic CMOS process. The STT-MRAM film stack is carefully designed to achieve both solder-reflow tolerance and short write pulse of 50nS. A merged reference scheme with reverse connected reference cells are proposed for read-disturb immunity. A read access time of 9nS is achieved from -40C to 125C and Vdd=0.8V±10%, making it suitable for high performance MCU applications. Silicon data measurement is presented to demonstrate a logic-process compatible, perpendicular STT-MRAM in 16nm FinFET CMOS process. The bit-error-rate has achieved zero fail-bit-count at 50-percentile for the 8Mb test-chip at wafer level.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123776490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Diamond Semiconductor Devices, state-of-the-art of material growth and device processing 金刚石半导体器件，最先进的材料生长和器件加工
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371947
H. Umezawa
{"title":"Diamond Semiconductor Devices, state-of-the-art of material growth and device processing","authors":"H. Umezawa","doi":"10.1109/IEDM13553.2020.9371947","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371947","url":null,"abstract":"Diamond is known as an ultimate semiconductor material because of its superior properties and it is expected to be employed in next-generation power electronic devices. Progress in wafer technology and device processing techniques have improved the performance of semiconductor devices. In this paper, state of the art of diamond semiconductor devices, especially power devices and harsh environmental devices including wafer technologies will be introduced.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123778175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wireless Power Transfer for Internet of Things 面向物联网的无线电力传输
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371927
Y. Kawahara, T. Sasatani
{"title":"Wireless Power Transfer for Internet of Things","authors":"Y. Kawahara, T. Sasatani","doi":"10.1109/IEDM13553.2020.9371927","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371927","url":null,"abstract":"Wireless power transfer and energy harvesting are essential to the realization of the Internet of Things (IoT). Design of wireless power transfer technology often requires the knowledge and the skill in electrical engineering, and it is not easy for IoT designers in information science. In addition, due to the diversity of the size and the power consumption of the target ‘things’, there is still no one-size-fits-all solution. In this paper, we introduce two projects enhances the easiness of the deployment while extending the transmission range. We believe that these system level improvements realized by electrical engineering and information science will increase the usability of the wireless power transmission systems.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121473432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Large scale plane-wave based density-functional theory simulations for electronic devices 基于密度泛函理论的电子器件大尺度平面波模拟
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372113
L. Wang, M. Ye, Y. Liu, X. Jiang
{"title":"Large scale plane-wave based density-functional theory simulations for electronic devices","authors":"L. Wang, M. Ye, Y. Liu, X. Jiang","doi":"10.1109/IEDM13553.2020.9372113","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372113","url":null,"abstract":"In this paper, we demonstrate that it is practical to use plane-wave based density functional theory (DFT) calculations to study a wide range of problems related to electronic devices like field-effect transistor (FET). Realistic crystalline-Si and amorphous-SiO2 interface is constructed to model the device. A divide and conquer linear scaling three-dimensional fragment method (LS3DF) together with a special Poisson solution scheme is used to solve the whole device system self-consistently under nonequilibrium condition. A special fully ab initio quantum transport calculation method is developed to simulate the current flow through the device. We also show that the plane-wave DFT is capable of studying the reliability dynamics rooted in oxide/interfacial defects including the Si-H bond breaking due to electron excitation.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122706081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers 基于嵌入式2T1R结构的MoS2和Si CMOS垂直堆叠3D集成在全晶圆上的演示
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371988
C. Su, M. K. Huang, K. S. Lee, V. Hu, Y. F. Huang, B. Zheng, C. Yao, N. Lin, K. Kao, T. Hong, P. Sung, C. Wu, T. Yu, K. Lin, Y. Tseng, C. L. Lin, Y. Lee, T. Chao, J. Y. Li, W. F. Wu, J. Shieh, Y. H. Wang, W. Yeh
{"title":"3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers","authors":"C. Su, M. K. Huang, K. S. Lee, V. Hu, Y. F. Huang, B. Zheng, C. Yao, N. Lin, K. Kao, T. Hong, P. Sung, C. Wu, T. Yu, K. Lin, Y. Tseng, C. L. Lin, Y. Lee, T. Chao, J. Y. Li, W. F. Wu, J. Shieh, Y. H. Wang, W. Yeh","doi":"10.1109/IEDM13553.2020.9371988","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371988","url":null,"abstract":"For the first time, a 3D stacking of MoS2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS2 /p+-Si structure showing high ON/OFF ratio of 106 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128068362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Advanced Node DTCO in the EUV Era EUV时代的高级节点DTCO
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371921
A. Wei, C. Wallace, M. Phillips, J. Knudsen, S. Chakravarty, M. Shamanna, R. Brain
{"title":"Advanced Node DTCO in the EUV Era","authors":"A. Wei, C. Wallace, M. Phillips, J. Knudsen, S. Chakravarty, M. Shamanna, R. Brain","doi":"10.1109/IEDM13553.2020.9371921","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371921","url":null,"abstract":"EUV lithography has finally made it into high-volume manufacturing and this has reset the approach to leading-edge Design Technology Co-Optimization. ArF immersion lithography multi-pass patterning was on course to push the technology design rules to be so restrictive, that design optimization would become a clear second priority. EUV lithography restores the balance between design optimization for performance, power, and area scale, along with technology optimization for yield and cost. However, due to the late introduction of EUV, this balance may be short-lived, and further rapid improvement in EUV lithography capability is highly anticipated.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Improved Model on Buried-Oxide Damage for Total-Ionizing-Dose Effect on HV SOI LDMOS 基于总电离剂量效应的HV SOI LDMOS埋氧化损伤改进模型
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9372012
Zhangyi’an Yuan, M. Qiao, Xinjian Li, Xin Zhou, Zhaoji Li, Bo Zhang
{"title":"An Improved Model on Buried-Oxide Damage for Total-Ionizing-Dose Effect on HV SOI LDMOS","authors":"Zhangyi’an Yuan, M. Qiao, Xinjian Li, Xin Zhou, Zhaoji Li, Bo Zhang","doi":"10.1109/IEDM13553.2020.9372012","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372012","url":null,"abstract":"The distribution of radiation induced positive oxide trapped charges (Not) in buried oxide (BOX) with different applied electric fields for high-voltage (HV) SOI LDMOS is investigated. In contrast to the traditional model which depends upon Not buildup near the interface that the field line points to, the verified experimental results in this work indicated that there are still a non-negligible set of Not generated in SOI/BOX interface even if the electric field plays a negative role (field line perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX). The improved model on BOX damage induced by TID considering this set of Not and its saturation effect is proposed and adopted in accurate simulated analysis to predict the post-irradiation device behavior. The mechanism of HV SOI LDMOS degradation during irradiation is also revealed. The radiation hardening LDMOS in this work keeps breakdown voltage above 120 V at D=500 krad(Si).","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114293370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MRAM DTCO and Compact Models MRAM DTCO和紧凑型车型
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371928
Jeehwan Song, Jianping Wang, C. Kim
{"title":"MRAM DTCO and Compact Models","authors":"Jeehwan Song, Jianping Wang, C. Kim","doi":"10.1109/IEDM13553.2020.9371928","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371928","url":null,"abstract":"Design-Technology Co-Optimization (DTCO) has become an important design methodology for making early decisions on technology, circuit, and system design parameters. This invited paper introduces various aspects of DTCO for MRAM development, ranging from SPICE compatible Magnetic Tunnel Junction (MTJ) device models, array level spin transfer torque magnetoresistive random access memory (STT-MRAM) power-performance-area (PPA) evaluation, scalability and variability studies of large-scale arrays, and novel read and write circuit techniques.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114456269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction 基于循环神经网络量子纠错的嵌入式存储技术的低温基准
2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI: 10.1109/IEDM13553.2020.9371912
Panni Wang, Xiaochen Peng, W. Chakraborty, A. Khan, S. Datta, Shimeng Yu
{"title":"Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction","authors":"Panni Wang, Xiaochen Peng, W. Chakraborty, A. Khan, S. Datta, Shimeng Yu","doi":"10.1109/IEDM13553.2020.9371912","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371912","url":null,"abstract":"Even at deep cryogenic temperature ~20 milli-Kevin, the qubit is fragile, therefore a feedback loop is needed to perform the quantum error correction (QEC). It is highly desirable to operate the QEC at 4K to minimize the thermal heat transfer between the physical qubits and the peripheral control circuitry. In this work, we propose implementing the surface code QEC circuitry with compute-in-memory (CIM) based recurrent neural network accelerator at 4K. To serve this purpose, we develop Cryo-NeuroSim, a device-to-system modeling framework that calibrate the transistor and interconnect parameters with experimental data at cryogenic temperature. Then we benchmark the QEC circuitry with SRAM technologies and optimize its energy-delay-product (EDP) with reengineered threshold voltage and supply voltage.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114878853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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