VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation最新文献

Emerging devices beyond CMOS: fundamentals, promises and challenges 超越CMOS的新兴器件:基本原理、前景和挑战

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch7

引用次数: 0

Two-dimensional material-based field-effect transistors for post-silicon electronics 后硅电子用二维材料场效应晶体管

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch8

Brajesh Rawat, R. Paily

{"title":"Two-dimensional material-based field-effect transistors for post-silicon electronics","authors":"Brajesh Rawat, R. Paily","doi":"10.1049/pbcs073f_ch8","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch8","url":null,"abstract":"The digital and analog performance of 2-D vdW-FETs has been investigated using the quantum-transport simulations. This work also presented a performance comparison between 2-D vdW-FETs and Si-MOSFET. It has found that MoS2 can deliver lower power consumption and higher speed for geometries corresponding to those of the 2028 node of the 2013 ITRS. On the other hand, WS2 -FET can provide better gate controllability, higher speed, and lower power consumption over 2-D vdW-FET for L g > 5 nm. However, in the deep nanometer range, the analog and digital performance metrics of 2-D vdW-FETs have found comparable to Si-MOSFET, even the intrinsic PDP of MoS2 - and WS2 -FET is marginally smaller than that of Si-MOSFET. Thus, single -layer TMD-FETs are certainly not the best option for post-silicon electronic, but the optimization of material geometry and an effective device design strategy can allow better gate controllability and performance improvement. Future studies in 2-D vdW-FETs should focus on understanding the interplay of scattering mechanisms due to substrate interactions or impurities to recognize roadblocks for next-generation flexible and transparent electronics.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128864880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High performing metal–oxide semiconductor thin-film transistors 高性能金属氧化物半导体薄膜晶体管

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch12

D. Kumar, J. Kettle

引用次数: 0

Low-voltage, low-power SRAM circuits using subthreshold design technique 采用亚阈值设计技术的低电压、低功耗SRAM电路

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch3

Anu Gupta, Priya Gupta, Abhijit R. Asati

引用次数: 0

Spintronics memory and logic: an efficient alternative to CMOS technology 自旋电子学存储器和逻辑:CMOS技术的有效替代品

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch10

V. Nehra, B. Kaushik

{"title":"Spintronics memory and logic: an efficient alternative to CMOS technology","authors":"V. Nehra, B. Kaushik","doi":"10.1049/pbcs073f_ch10","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch10","url":null,"abstract":"Intel declared 2016 as the end of Moore's prediction. Researchers and academicians are exploring other alternatives to fulfill the latency between the processor and memory system. A universal memory is required that can be used at the various levels of memory hierarchy. STT-MRAM has shown the promising features to be used at various levels of memory hierarchy. In this chapter, we discussed the GMR, TMR, and STT as the basic phenomena required for STT-MRAM reading and writing. Conversion of charge current to spin-polarized current is explained with the help of Bloch states of different symmetries. I-MTJ and P-MTJ are explained using key performance parameters such as thermal stability and critical current. Working of STT-MRAM bit cell is discussed using NMOS transistor as an access device. Framework for low power hybrid MTJ/CMOS circuits is explained using PCSA, CMOS logic tree, and nonvolatile input store in terms of relative magnetization state of MTJs. STT-MRAM faces the challenges of high write energy, reliability, and read disturbance due to common read and write path. To mitigate these issues, SOT-based device and fast-switching mechanism VCMA has been suggested. Finally, based on the performance of STT-MRAM, it can be projected that low-power operations can be achieved using STT-MRAM as a working memory. Further, high-speed and low-power operations can be attained with hybrid MTJ/CMOS nonvolatile core circuits. The recent developments in the spintronics field have opened the door for energy-saving and high-performance electronics from device level to circuit level.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115541657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-voltage analog signal processing 低压模拟信号处理

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch1

Ahlad Kumar, S. Rajput

引用次数: 0

Design and analysis of memristor-based DRAM cell for low-power application 基于忆阻器的低功耗DRAM单元设计与分析

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch4

A. Raman, Deep Shekhar, Ravi Ranjan, Suchitra Kumari

{"title":"Design and analysis of memristor-based DRAM cell for low-power application","authors":"A. Raman, Deep Shekhar, Ravi Ranjan, Suchitra Kumari","doi":"10.1049/pbcs073f_ch4","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch4","url":null,"abstract":"Using conventional memory technologies, for example, static random access memory (RAM) (SRAM), dynamic RAM (DRAM) and flash memory, it is difficult to fulfill the market requirements for higher density and lower power dissipation [1]. Therefore, semiconductor organizations are thinking that it is difficult to supply the expanding market interest for the higher density and lower power nonvolatile memories [2]. The recent invention of memristor device has given hope to semiconductor organizations by offering a less demanding approach to expand the density by utilizing the current fabrication technology [3]. This is conceivable on the grounds that memristor devices just require two terminals to work, which utilize less wafer space, reduce the complexity of circuit interconnections and encourage highdensity integration when used as a part of crossbar structures [4-7]. Besides all these features of memristor, it also has some additional characteristics like low power and non-volatility [8]. But the main limitation of the memristor-based memory cell is its slow write time access [9]. Transmission gate is capable of providing rail-to-rail swing and can easily pass both logic “0” and logic “1” [10]. These advantages help to overcome the problem of slow write time access of memristor. The objective of this chapter is to understand what a memristor is and how can a memristor be modeled for its current-voltage (I-V) characteristics. Further, this chapter deals with the concepts of transmission gates, then using the designed memristor and transmission gates, a DRAM cell was designed. The designed memory cell was simulated using HSPICE tool. The result shows that the memristor-based DRAM cell can replace the conventional memory cell in future to achieve higher density and lower power dissipation.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"2 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133742461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Composite PFD based low-power, low noise, fast lock-in PLL 基于复合PFD的低功耗，低噪声，快速锁定锁相环

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch6

B. Kailath, Kottampara Kuppalath Majeed

引用次数: 1

CNTFETs: modelling and circuit design cntfet:建模和电路设计

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch13

Amandeep Singh, M. Khosla, B. Raj

{"title":"CNTFETs: modelling and circuit design","authors":"Amandeep Singh, M. Khosla, B. Raj","doi":"10.1049/pbcs073f_ch13","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch13","url":null,"abstract":"In this book chapter, a brief introduction is provided to CNTs, its material science, modelling, simulation and circuit application. CNTs are explored from electronic properties as the nature of conduction, i.e., metallic and semiconducting. Chirality is explained, which is responsible for basic parameters calculations like diameter and bandgap. Considering the excellent characteristics of CNT, how they are used as channel materials in MOSFETs is discussed along with the type of CNTFET. The physics behind the working of CNTFET is explained for every type along with advantages and disadvantages of device type. Since CNTFETs have many challenges for future devices, the most important challenge of doping is discussed along with the novel solution, i.e., electrostatic doping. The concept of electrostatic doping is explained with the help of a band diagram as how the biases at polarity gates are used to shift the bands the same as in conventional doping. The characteristics of an ED device are compared with a conventional doped device in order to get better understanding and advantage of the device. The only available benchmark simulation tool for CNTFETs is discussed along with the model used in calculations of drain current. Also the different types of CNTFETs are simulated in this tool, and the characteristics are shown. Apart from conventional CNTFET, ED CNTFET is also simulated in the tool in order to check the results. Along with numerical tool for simulation, the various approaches that can be used to model the device are discussed. The equations are explained with device physics for both conventional CNTFET and ED CNTFET. Lastly, the circuit applications are discussed ranging from analog to digital applications.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121278806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a novel tunnel FET for low-power applications 用于低功耗应用的新型隧道场效应管的设计

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation Pub Date : 2019-09-27 DOI: 10.1049/pbcs073f_ch5

B. Bhowmick

引用次数: 1