{"title":"Negative bias temperature instability (NBTI) aware low leakage circuit design","authors":"V. Sharma, M. Pattanaik","doi":"10.1049/pbcs073f_ch2","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch2","url":null,"abstract":"The tremendous scaling of the semiconductor devices is producing the high-density integrated circuits (ICs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the basic building blocks for the ICs. The lower area requirement with increased numbers of devices on a substrate makes it an interesting field of very-large-scale integration (VLSI) design. The reliability of the logic circuits is the concern issue in modern-era electronics. Reliability affects the overall performance of the logic circuits and possibility to the failure of the semiconductor devices. Negative bias temperature instability (NBTI) degradation is the major concern in ultra-deep submicron (DSM) regime. The negative threshold voltage of PMOS device when shifted in NBTI effect causes performance degradation over the time. NBTI degradation is the aging effect for PMOS device. This chapter presents the overview of NBTI effect and its possible solution.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126055011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Theory and modelling of spin-transfer-torque based electronic devices","authors":"A. Singha","doi":"10.1049/pbcs073f_ch9","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch9","url":null,"abstract":"In this chapter, we have mainly discussed STT-based classical devices. However, the promise of spin-based computing extends far beyond the devices discussed in this chapter. Some of the other promising technologies that can be employed for spin-based classical computation include quantum dots, quantum Hall bars, spins trapped in nitrogen vacancy centers, etc. Such technologies are still in their infancy and a lot of progress need to be made before such technologies may be incorporated in consumer level systems.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117032034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tunneling field effect transistors for energy efficient digital, RF and power management circuit designs enabling IoT edge computing platforms","authors":"A. Japa, T. Nagateja, R. Vaddi","doi":"10.1049/pbcs073f_ch11","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch11","url":null,"abstract":"In this chapter, we have studied the device structure and characteristics of TFETs for energy-efficient circuit design useful for IoT edge computing platforms. TFET shows better electrical characteristics in terms of SS, transconductance, current efficiency, and device FoM. Unlike MOSFETs, TFETs exhibit distinct electrical properties like ambipolar conduction and unidirectional current conduction. TFET-based digital logic gates and buffer circuits are analyzed and benchmarked with Si FinFET for energy efficiency. TFETs outperform FinFET designs and achieve better energy efficiency at low V DD . Due to the high ON-current of the devices, TFET RO reports a frequency of 21 GHz, whereas FinFET RO achieves 13 GHz under similar design conditions. It was shown that due to the enhanced Miller capacitance effect in TFETs, transient characteristics of TFET RO suffers from high overshoots and undershoots. We further looked into TFET-based VCRO design wherein TFET design achieves wide tuning range compared to FinFET designs. Finally, we demonstrate TFET-based DLDO achieving low quiescent current with high-energy efficiency. In summary, TFETs have some unique characteristics that make them an ideal candidate for low voltage IoT platforms with specific design challenges to circuit and system design community as discussed.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122993634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}