{"title":"Two-dimensional material-based field-effect transistors for post-silicon electronics","authors":"Brajesh Rawat, R. Paily","doi":"10.1049/pbcs073f_ch8","DOIUrl":null,"url":null,"abstract":"The digital and analog performance of 2-D vdW-FETs has been investigated using the quantum-transport simulations. This work also presented a performance comparison between 2-D vdW-FETs and Si-MOSFET. It has found that MoS2 can deliver lower power consumption and higher speed for geometries corresponding to those of the 2028 node of the 2013 ITRS. On the other hand, WS2 -FET can provide better gate controllability, higher speed, and lower power consumption over 2-D vdW-FET for L g > 5 nm. However, in the deep nanometer range, the analog and digital performance metrics of 2-D vdW-FETs have found comparable to Si-MOSFET, even the intrinsic PDP of MoS2 - and WS2 -FET is marginally smaller than that of Si-MOSFET. Thus, single -layer TMD-FETs are certainly not the best option for post-silicon electronic, but the optimization of material geometry and an effective device design strategy can allow better gate controllability and performance improvement. Future studies in 2-D vdW-FETs should focus on understanding the interplay of scattering mechanisms due to substrate interactions or impurities to recognize roadblocks for next-generation flexible and transparent electronics.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/pbcs073f_ch8","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The digital and analog performance of 2-D vdW-FETs has been investigated using the quantum-transport simulations. This work also presented a performance comparison between 2-D vdW-FETs and Si-MOSFET. It has found that MoS2 can deliver lower power consumption and higher speed for geometries corresponding to those of the 2028 node of the 2013 ITRS. On the other hand, WS2 -FET can provide better gate controllability, higher speed, and lower power consumption over 2-D vdW-FET for L g > 5 nm. However, in the deep nanometer range, the analog and digital performance metrics of 2-D vdW-FETs have found comparable to Si-MOSFET, even the intrinsic PDP of MoS2 - and WS2 -FET is marginally smaller than that of Si-MOSFET. Thus, single -layer TMD-FETs are certainly not the best option for post-silicon electronic, but the optimization of material geometry and an effective device design strategy can allow better gate controllability and performance improvement. Future studies in 2-D vdW-FETs should focus on understanding the interplay of scattering mechanisms due to substrate interactions or impurities to recognize roadblocks for next-generation flexible and transparent electronics.