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1991 Proceedings, International Conference on Wafer Scale Integration最新文献

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Comparing monolithic and hybrid WSI massively parallel processing modules for cost-effective real-time signal and data processing 比较单片和混合WSI大规模并行处理模块的成本效益实时信号和数据处理
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151716
R. Lea
{"title":"Comparing monolithic and hybrid WSI massively parallel processing modules for cost-effective real-time signal and data processing","authors":"R. Lea","doi":"10.1109/ICWSI.1991.151716","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151716","url":null,"abstract":"It is demonstrated that wafer-scale-integration associative string processor (WSI ASP) module components offer a 150-800 times improvement in TOPS (tera operations per second)/ft/sup 3/, a 13 times improvement in GOPS (giga operations per second)/W and a 14-44 times improvement in MOPS (mega operations per second)/$ over VLSI components. For all three figures-of-merit monolithic-WSI ASP modules have an advantage over hybrid WSI ASP modules. In addition, the inherent defect-tolerance in the manufacture of monolithic-WSI ASP modules offers fault-tolerance in service, which the hybrid-WSI ASP could only match with an increase in chip size and cost. Lastly, and significantly for the future, the precisely regular layout of monolithic-WSI ASP wafers renders them excellent candidates for highly-compact 3-D packaging techniques, offering significant improvements in TOPS/ft/sup 3/ which could not be achieved with hybrid-WSI.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Layout, design finish and packaging of a redundant signal multiprocessor architecture with WSI dimensions 具有WSI尺寸的冗余信号多处理器架构的布局、设计完成和封装
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151720
T. Link, W. Teich, A. Werner
{"title":"Layout, design finish and packaging of a redundant signal multiprocessor architecture with WSI dimensions","authors":"T. Link, W. Teich, A. Werner","doi":"10.1109/ICWSI.1991.151720","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151720","url":null,"abstract":"An ASIC (application specific integrated circuit) design flow for the realization of a multiprocessor structure has been successfully established and verified. This design flow includes standard tools and project-specific extensions, especially for verification tasks and preparation of WSI (wafer scale integration) data fractioning. The achieved layout and factory finishing method 'nonoverlapping hierarchy' uses the regular multiproject wafer approach of an ASIC direct-write E-beam foundry and seems to have no area limits within the available wafer dimensions. Due to the extensive utilization of standard tools and flows wherever possible, a fast design and fabrication process for prototypes is guaranteed. This leads to a minimization of manpower, time, and processing costs.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114230815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Combining switch and site yields for soft-configurable WSI 结合开关和站点产生软配置WSI
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151702
M. Blatt
{"title":"Combining switch and site yields for soft-configurable WSI","authors":"M. Blatt","doi":"10.1109/ICWSI.1991.151702","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151702","url":null,"abstract":"The configuration requirements of a soft-configurable pipelined memory are described. Monte Carlo simulations show that wafer yield dependence on high switch yields can be reduced substantially using switch path bypasses and/or spare columns. These simulations combine the effects of switch and site failures in ways that cannot easily be captured using simpler analytic models, due to interdependencies between the effects of switch and site failures on system configuration.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122972592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient reconfiguration algorithms for degradable VLSI/WSI arrays 可降解VLSI/WSI阵列的高效重构算法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151705
S. Kuo, Ing-Yi Chen
{"title":"Efficient reconfiguration algorithms for degradable VLSI/WSI arrays","authors":"S. Kuo, Ing-Yi Chen","doi":"10.1109/ICWSI.1991.151705","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151705","url":null,"abstract":"A systematic method for reconfiguration in VLSI/WSI (wafer scale integration) arrays using the degradation approach for yield enhancement is presented. Based on the bipartite graph representation of faulty cells in a reconfigurable host array, the problem of finding a maximum fault-free target array is shown to be equivalent to finding a restricted independent set of vertices in the graph models. Three constraints on the row and column reconfigurability are considered. The complexity is analyzed and heuristic algorithms are developed for variations of the problem under the three constraints. These algorithms have been implemented in C and experimental results were collected which demonstrate the efficiency of the proposed approaches.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129792404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
Multiple voting systolic array 多重投票收缩数组
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151692
H. Mori, J. Kambara
{"title":"Multiple voting systolic array","authors":"H. Mori, J. Kambara","doi":"10.1109/ICWSI.1991.151692","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151692","url":null,"abstract":"A model of the multiple voting systolic array is proposed. The proposed fault tolerant technique uses majority decision by voting, without reconfiguration. As an example, a DFT (discrete Fourier transform) implementation of a triple voting systolic array is presented. It is shown that area redundancy is small and dynamic fault recovery is possible. It is believed that proposed fault-tolerant architecture is suitable for WSI (wafer-scale integration) processors.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122813530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A rapid prototype wafer scale system design for signal and data processing 一种用于信号和数据处理的快速原型晶圆级系统设计
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151698
D. Landis, H. Brown, T. Sanders, M. Shahsavari, J. Hadjilogiou, R. Shankar
{"title":"A rapid prototype wafer scale system design for signal and data processing","authors":"D. Landis, H. Brown, T. Sanders, M. Shahsavari, J. Hadjilogiou, R. Shankar","doi":"10.1109/ICWSI.1991.151698","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151698","url":null,"abstract":"The authors describe a WSI (wafer scale integration) rapid prototype system design project. Applications which can be implemented as WSI systems are being developed at three universities (alpha sites). A single WSI design is being developed which can be rapidly restructured to meet the system requirements of each university. A system design verification approach that involves a common CAD (computer-aided design) tool base for high-level modeling has been defined by the multiuniversity team. Each alpha site is developing high-level models for their architecture using VHDL (VHSIC hardware description language), and the physical wafer structure will be automatically mapped to the wafer from the VHDL model.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115439230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rotary spare replacement redundancy for tree architecture WSIs 树形结构wsi的旋转备件替换冗余
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151700
N. Tsuda
{"title":"Rotary spare replacement redundancy for tree architecture WSIs","authors":"N. Tsuda","doi":"10.1109/ICWSI.1991.151700","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151700","url":null,"abstract":"The author proposes rotary spare replacement redundancy (RSRR) for defect tolerance in tree architecture WSIs. The main feature of the RSRR is that it can be applied in element groups of a subroot element and its leaf elements on every neighboring two stages, using a simple switching scheme based on k-out-of-n redundancy. Especially, it can be applied to hierarchical redundancy, which is advantageous in terms of spare effectiveness, redundancy coverage, and replacement control simplicity. The effectiveness of the proposed redundancy is demonstrated through estimates based on the design of an eight-stage binary tree merger WSI (wafer scale integration) with a three-level hierarchical redundancy configuration.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123376367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A MIMD based multiprocessor architecture for real-time image processing suitable for a monolithic redundant realization 一种适合于单片冗余实现的基于MIMD的实时图像处理多处理器体系结构
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151694
H. Jeschke, T. Wehberg, K. Volkers
{"title":"A MIMD based multiprocessor architecture for real-time image processing suitable for a monolithic redundant realization","authors":"H. Jeschke, T. Wehberg, K. Volkers","doi":"10.1109/ICWSI.1991.151694","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151694","url":null,"abstract":"A novel MIMD (multiple instruction multiple data) based multiprocessor architecture consisting of multiple processing elements (PE) has been developed for real-time image processing. Each PE contains an arithmetic processing unit adapted to convolution-like low-level operations and a high-level and control processor. A high-speed random access to local image data is provided by two local input memories and an I/O and feedback unit. This architecture has a high regularity at the task level which is suitable for a WSI (wafer scale integration) implementation. The main parts of a PE have been realized as VLSI test chips providing a computational rate of up to 400 MOPS for one PE.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126688290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Testing of very large systems: a hierarchical approach to fault coverage evaluation 非常大的系统的测试:故障覆盖评估的分层方法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151729
F. Distante, M. Sami, D. Sciuto
{"title":"Testing of very large systems: a hierarchical approach to fault coverage evaluation","authors":"F. Distante, M. Sami, D. Sciuto","doi":"10.1109/ICWSI.1991.151729","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151729","url":null,"abstract":"The authors consider general, uncommitted systems whose only particular characteristic is that of affording a hierarchical, structured organization. For such systems, they propose a graph-based representation of the testing problem. First, it is seen how such representation makes it possible to define the relationship between test vectors and faults at one abstraction level: then, a multiple-level extension is introduced. This multiple-level representation is used to evaluate the limits of test coverage that can be achieved when higher levels of abstraction are used and to introduce the definition of test procedures at a high abstraction level.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126799449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect tolerance and yield for a wafer scale FFT processor system 晶圆级FFT处理器系统的缺陷容限与良率
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151696
V. Jain, H. Hikawa, E. Swartzlander
{"title":"Defect tolerance and yield for a wafer scale FFT processor system","authors":"V. Jain, H. Hikawa, E. Swartzlander","doi":"10.1109/ICWSI.1991.151696","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151696","url":null,"abstract":"A wafer scale system for frame-by-frame computation of the fast Fourier-transform (FFT) is described. It is based on an eight-point FFT wafer design, which uses two types of cells, a multiply-subtract-add (MSA) cell and a coefficient ROM cell. Systematic repetition of these cells and the interconnect forms the physical wafer. The cells are designed for high performance and testability. For successive 512-point frames, the throughput is estimated at 20 million samples/s. Innovations in preplacement have reduced the traffic in the interconnect channels while enhancing the reconfigurability in the presence of defects. Estimates of wafer yield using a new model for harvesting probability are also presented.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133086294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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