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1991 Proceedings, International Conference on Wafer Scale Integration最新文献

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WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing WSI收缩网络:用于基于ulsi的并行计算的有源硅电路板功能
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151726
S. Tewksbury
{"title":"WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing","authors":"S. Tewksbury","doi":"10.1109/ICWSI.1991.151726","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151726","url":null,"abstract":"The evolution of silicon to 0.25- mu m technologies will yield very powerful, single-chip ULSI arrays of high-performance processors and high-capacity wafer-scale memories. The very compact, distributed computing systems which result will require very-high-performance communication networks, scaled to the much smaller size and more monolithic realization of future distributed systems. Multichip systems, using such ULSI processor arrays, suggest wafer-level, monolithic versions of their communication networks, extending current passive 'silicon circuit boards' to silicon wafer area networks. Since VLSI constraints are similar to those of systolic computational arrays, the wafer-level networks might be called systolic communication networks. The author discusses some of the basic design issues facing these communication networks, emphasizing the importance of very high information transfer rates and the objective of achieving virtual, point-to-point interconnections through a switched network.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"115 11 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
WSI interconnect issues: practical experience gained on the WASP project WSI互连问题:在WASP项目中获得的实践经验
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151725
S. Hedge, I. Jalowiecki, R. Lea
{"title":"WSI interconnect issues: practical experience gained on the WASP project","authors":"S. Hedge, I. Jalowiecki, R. Lea","doi":"10.1109/ICWSI.1991.151725","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151725","url":null,"abstract":"The problems of external interfacing and internal interconnection for WSI (wafer scale integration) devices are considered. In particular, the WASP (WSI associative string processor) 2A device is examined in detail, and practical results are presented. Analysis of the experimental on-wafer interconnection included on WASP 2A has shown that, given simple layout precautions, a high yield can be obtained for non-defect-tolerant buses. However, it is also apparent that practical experience concerning the defect modes of these buses is important in the design of any defect tolerance strategy for yield improvement. Results from using WASP 2A have shown that defect and fault tolerance may be cost-effectively implemented at the level of the wafer interface, allowing for the recovery from defects and in-service failures, and substantially increasing the projected yield of this crucial wafer component.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133403041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets 线性阵列结构对WSI实现神经网络容错特性的影响
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151704
F. Distante, M. Sami, R. Stefanelli, G. Storti Gajani
{"title":"Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets","authors":"F. Distante, M. Sami, R. Stefanelli, G. Storti Gajani","doi":"10.1109/ICWSI.1991.151704","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151704","url":null,"abstract":"A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, particular care is taken to minimize area requirements while maximizing throughput and parallelism. The architecture is well suited to support, with minimal additional changes, fault/defect tolerance with respect to faults located in the PEs (processing elements), switches, or buses.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114639186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Physical design of the MUSE wafer-scale circuit MUSE晶圆级电路的物理设计
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151689
A. N. Anderson, C. Woodward
{"title":"Physical design of the MUSE wafer-scale circuit","authors":"A. N. Anderson, C. Woodward","doi":"10.1109/ICWSI.1991.151689","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151689","url":null,"abstract":"MUSE is a wafer-scale adaptive nulling processor which is being implemented using the restructurable VLSI techniques and design tools. The authors describe the physical design of the wafer with emphasis on interconnect redundancy and design for testability during the restructuring process. Power distribution and the wafer floorplan and packaging are also discussed.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124049607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A generalized Poisson based model for defect spatial distribution in WSI WSI缺陷空间分布的广义泊松模型
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151709
A. Tyagi, M. Bayoumi
{"title":"A generalized Poisson based model for defect spatial distribution in WSI","authors":"A. Tyagi, M. Bayoumi","doi":"10.1109/ICWSI.1991.151709","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151709","url":null,"abstract":"Discusses the use of the modified generalized Poisson binomial limit in modeling defect spatial distribution in WSI (wafer scale integration) and large-area VLSI chips. This model demonstrates the usefulness of generalized Poisson distributions for effectively taking into account the issues of the distribution of clusters and cluster sizes. The strength of the proposed model lies in its simplicity and its close adherence to the forms of defect patterns on a wafer. The model shows excellent fits to the data from simulated wafer maps with high clustering of defects. It also exhibits good fits to data from wafers with small-area, highly dispersed clusters.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130454412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and parallel testing of wafer scale linear arrays with high harvest rates 高收获率晶圆级线性阵列的设计与并行测试
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151728
M. Chang, W. Fuchs
{"title":"Design and parallel testing of wafer scale linear arrays with high harvest rates","authors":"M. Chang, W. Fuchs","doi":"10.1109/ICWSI.1991.151728","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151728","url":null,"abstract":"Design for high harvest rates and parallel on-wafer diagnosis of linear arrays are described. A generalized loop-based approach to defect-tolerant wafer scale linear arrays is presented. In terms of harvest rate, the loop-based approach is significantly better than the traditional spiral approaches. Similar to the spiral approaches, the loop-based approach guarantees a fixed propagation delay between any logically consecutive cells after reconfiguration, independent of the fault distribution. However, the propagation delay is larger than that of the spiral approaches. Simulation-based harvest rates for four loop-based approaches are described. Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is also presented.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128187597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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