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1991 Proceedings, International Conference on Wafer Scale Integration最新文献

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Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation 用于FFT计算的可重构WSI结构并发错误检测和故障定位
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151695
F. Lombardi, J. Muzio
{"title":"Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation","authors":"F. Lombardi, J. Muzio","doi":"10.1109/ICWSI.1991.151695","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151695","url":null,"abstract":"Presents a novel approach for concurrent error detection and location in homogeneous VLSI/WSI (wafer scale integration) architectures for the computation of the complex N-point fast Fourier transform. The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analyzed with respect to functional and physical faults. Overhead issues for hardware and timing are addressed.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130484222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Silicon substrate test structures for hybrid wafer scale technology 混合晶圆规模技术的硅衬底测试结构
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151714
M. J. Davies, A. Munns, D.J. Pedder
{"title":"Silicon substrate test structures for hybrid wafer scale technology","authors":"M. J. Davies, A. Munns, D.J. Pedder","doi":"10.1109/ICWSI.1991.151714","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151714","url":null,"abstract":"The authors explore the variety of test structures that may be used in the fabrication and assembly of silicon substrate multichip modules (MCMs) that aim at wafer scale complexity levels, with particular reference to their technological role. It is pointed out that a comprehensive set of test structures has been devised that provides yield, performance, and reliability information for silicon substrate MCM development activities. Some of these structures are well suited as compact, drop-in process monitors in functional MCM substrate manufacture. Built-in chip self test, scan path interrogation of the on-chip and substrate interconnections for defect location, circuit redundancy, reconfiguration and chip network techniques could all have some place in the realization of advanced MCMs of wafer scale complexity levels.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114066654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new approach to implement a defect tolerant power distribution network in WSI circuits 一种在WSI电路中实现容错配电网络的新方法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151718
M. Yung, M. J. Little
{"title":"A new approach to implement a defect tolerant power distribution network in WSI circuits","authors":"M. Yung, M. J. Little","doi":"10.1109/ICWSI.1991.151718","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151718","url":null,"abstract":"An efficient approach for implementing a defect-tolerant power distribution network suitable for WSI (wafer scale integration) circuits is proposed. The network is not segmented but relies on a thermal imaging technique for defect localization and laser cutting for defect isolation. Power bus designs for this approach are described. Preliminary, experimental results have verified the design concepts.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A self-testing and self-diagnostic systolic array cell for signal processing 一种用于信号处理的自检测和自诊断收缩阵列单元
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151699
C.-i.H. Chen, R. Smith
{"title":"A self-testing and self-diagnostic systolic array cell for signal processing","authors":"C.-i.H. Chen, R. Smith","doi":"10.1109/ICWSI.1991.151699","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151699","url":null,"abstract":"A built-in self test (BIST) method for a systolic array controller chip/multiplier-accumulator chip (SAC/MAC) was used to generate the signatures for all combinational blocks of each cell in parallel. The BIST is combined with a scan path design; therefore, all registers in the array cells are connected as a scan chain and all signatures are shifted out by this scan chain to be compared with a previously generated fault-free signature. Thus, the signature generated by the BIST circuitry determines the status of each cell (fault-free or faulty). The self-diagnostic capabilities were then incorporated into the BIST SAC/MAC cell to solve the problem of the long testing time caused by the long time required to scan out the test results when large arrays are used. Although incorporating BIST into the SAC/MAC cell made the array more testable, some redesign had to be done. The major change was using one chip instead of two.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124452337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An overview and analysis of 3D WSI 三维WSI的概述与分析
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151719
J. F. Mcdonald
{"title":"An overview and analysis of 3D WSI","authors":"J. F. Mcdonald","doi":"10.1109/ICWSI.1991.151719","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151719","url":null,"abstract":"The author reviews the early trends in 3-D WSI (wafer scale integration) and examines recent breakthroughs in technology to assess the viability of 3-D. It is concluded that this option is rich with possibility for the designer. However, not every architecture can benefit equally from this packaging approach. An attempt is made to quantify this impact by computing an average wire-shortening effect from 3-D partitioning, but even this average improvement is pessimistic if the given architecture is such that the most critical paths can all be placed on the vertical wiring runs in the stack, depending on the vertical spacing of the wafers.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134046395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A fast router and placement algorithm for wafer scale integration and wafer scale hybrid packaging 一种用于晶圆规模集成和晶圆规模混合封装的快速路由器和布局算法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151730
J. McDonald, B. Donlan, M. Russinovich, R. Philhower, K.S. Nah, H. Greub
{"title":"A fast router and placement algorithm for wafer scale integration and wafer scale hybrid packaging","authors":"J. McDonald, B. Donlan, M. Russinovich, R. Philhower, K.S. Nah, H. Greub","doi":"10.1109/ICWSI.1991.151730","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151730","url":null,"abstract":"The authors describe an algorithm developed for discretionary wafer routing needed for wafer scale integration (WSI) or multichip packaging. A very fast multilayer line probe router has been developed and implemented. The router uses a collection of depth-first heuristics to provide an extremely fast route with exceptional wiring quality and very high completion rate. The search algorithms and data structures are significantly different from those of D. Hightower (1969). These differences make it possible to route the special kinds of wiring needed for WSI in under a minute of VAX 6410 CPU time in many cases. Such a high-speed router will be necessary when line routing is to proceed at wafer throughput rates for fabrication.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121548624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Clock distribution strategies for WSI: a critical survey WSI的时钟分布策略:一项关键调查
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151727
D. Keezer, V. Jain
{"title":"Clock distribution strategies for WSI: a critical survey","authors":"D. Keezer, V. Jain","doi":"10.1109/ICWSI.1991.151727","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151727","url":null,"abstract":"The authors review the available methods for clock distribution design which have been used at the VLSI level and discuss the adjustments necessary for WSI (wafer scale integration) design. It is pointed out that much work has been reported regarding methods for clock distribution design for VLSI, and it is noted that these techniques can be applied to WSI with appropriate adjustments made for longer signal paths, higher capacitance, higher resistance, and higher fanout. The added complexity of potential alternate paths and associated alternate RC values must be considered when restructurable WSI circuits are clocked at high frequency. Resistance associated with the discretionary link process can make a significant contribution to the relevant delay calculations.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133710232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Yield considerations in the design of WASP3 WASP3设计中的屈服考虑
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151712
H. Bolouri, R. Lea
{"title":"Yield considerations in the design of WASP3","authors":"H. Bolouri, R. Lea","doi":"10.1109/ICWSI.1991.151712","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151712","url":null,"abstract":"Addresses yield modeling considerations in the development of the WASP (WSI associative string processor) architecture, floor plan, and defect-tolerance strategy. A fully parameterized, detailed yield model for WASP devices is presented, and the implications of various design options for device yield are analyzed. The WASP architecture has been shown to be capable of yields well in excess of the target of 50% for 8192-APE WASP devices.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114096722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Universal switching network: application to a WSI SIMD array 通用交换网络:应用到一个WSI SIMD阵列
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151724
A. Boubekeur, J. Patry, G. Saucier, J. Trilhe
{"title":"Universal switching network: application to a WSI SIMD array","authors":"A. Boubekeur, J. Patry, G. Saucier, J. Trilhe","doi":"10.1109/ICWSI.1991.151724","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151724","url":null,"abstract":"A wafer scale SIMD (single-instruction multiple-data) array of 5760 elementary one-bit processors dedicated to image processing and called ELSA (European Large SIMD Array) has been implemented. At the end of manufacturing, a cartography of good elements on the wafer is established. This cartography is given as input to the reconfiguration software which defines the best array it can construct in terms of performance and size. The universal switching network allowing this reconfiguration at a chip level is described. The originality of the switching network is the ability to cope with hierarchical design and the ability to be controlled and programmed externally and serially from the I/O pads. The soft programming of the paths to construct the target 2-D array is examined. The switch programming is effectively done in spite of defective switches, which is possible because of the external control of the switching array. The tree and path covering methods have been implemented in C; both give a good solution in a short time.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123730801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A reconfigurable cube-connected cycles architecture for wafer scale integration 用于晶圆规模集成的可重构立方体连接周期架构
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151693
N. Tzeng
{"title":"A reconfigurable cube-connected cycles architecture for wafer scale integration","authors":"N. Tzeng","doi":"10.1109/ICWSI.1991.151693","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151693","url":null,"abstract":"Proposes a novel reconfigurable architecture for the cube-connected cycles (CCC) implemented by wafer scale integration (WSI) technology. This design is aimed at maintaining the full rigid structure of the CCC in the presence of manufacturing defects. The spare PEs (processing elements), which are added to every building block of the system, can be shared by the PEs in immediate nearby blocks or be used to substitute defective PEs in distant blocks. As a result, the design utilizes spares more effectively than earlier designs in which spares in a block can be used solely by PEs within the same block, resulting in far better yield improvement.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126231017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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