Clock distribution strategies for WSI: a critical survey

Abstract

The authors review the available methods for clock distribution design which have been used at the VLSI level and discuss the adjustments necessary for WSI (wafer scale integration) design. It is pointed out that much work has been reported regarding methods for clock distribution design for VLSI, and it is noted that these techniques can be applied to WSI with appropriate adjustments made for longer signal paths, higher capacitance, higher resistance, and higher fanout. The added complexity of potential alternate paths and associated alternate RC values must be considered when restructurable WSI circuits are clocked at high frequency. Resistance associated with the discretionary link process can make a significant contribution to the relevant delay calculations.<>