{"title":"通用交换网络:应用到一个WSI SIMD阵列","authors":"A. Boubekeur, J. Patry, G. Saucier, J. Trilhe","doi":"10.1109/ICWSI.1991.151724","DOIUrl":null,"url":null,"abstract":"A wafer scale SIMD (single-instruction multiple-data) array of 5760 elementary one-bit processors dedicated to image processing and called ELSA (European Large SIMD Array) has been implemented. At the end of manufacturing, a cartography of good elements on the wafer is established. This cartography is given as input to the reconfiguration software which defines the best array it can construct in terms of performance and size. The universal switching network allowing this reconfiguration at a chip level is described. The originality of the switching network is the ability to cope with hierarchical design and the ability to be controlled and programmed externally and serially from the I/O pads. The soft programming of the paths to construct the target 2-D array is examined. The switch programming is effectively done in spite of defective switches, which is possible because of the external control of the switching array. The tree and path covering methods have been implemented in C; both give a good solution in a short time.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Universal switching network: application to a WSI SIMD array\",\"authors\":\"A. Boubekeur, J. Patry, G. Saucier, J. Trilhe\",\"doi\":\"10.1109/ICWSI.1991.151724\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wafer scale SIMD (single-instruction multiple-data) array of 5760 elementary one-bit processors dedicated to image processing and called ELSA (European Large SIMD Array) has been implemented. At the end of manufacturing, a cartography of good elements on the wafer is established. This cartography is given as input to the reconfiguration software which defines the best array it can construct in terms of performance and size. The universal switching network allowing this reconfiguration at a chip level is described. The originality of the switching network is the ability to cope with hierarchical design and the ability to be controlled and programmed externally and serially from the I/O pads. The soft programming of the paths to construct the target 2-D array is examined. The switch programming is effectively done in spite of defective switches, which is possible because of the external control of the switching array. The tree and path covering methods have been implemented in C; both give a good solution in a short time.<<ETX>>\",\"PeriodicalId\":413164,\"journal\":{\"name\":\"1991 Proceedings, International Conference on Wafer Scale Integration\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-01-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1991 Proceedings, International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1991.151724\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991 Proceedings, International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1991.151724","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Universal switching network: application to a WSI SIMD array
A wafer scale SIMD (single-instruction multiple-data) array of 5760 elementary one-bit processors dedicated to image processing and called ELSA (European Large SIMD Array) has been implemented. At the end of manufacturing, a cartography of good elements on the wafer is established. This cartography is given as input to the reconfiguration software which defines the best array it can construct in terms of performance and size. The universal switching network allowing this reconfiguration at a chip level is described. The originality of the switching network is the ability to cope with hierarchical design and the ability to be controlled and programmed externally and serially from the I/O pads. The soft programming of the paths to construct the target 2-D array is examined. The switch programming is effectively done in spite of defective switches, which is possible because of the external control of the switching array. The tree and path covering methods have been implemented in C; both give a good solution in a short time.<>