Yield considerations in the design of WASP3

Abstract

Addresses yield modeling considerations in the development of the WASP (WSI associative string processor) architecture, floor plan, and defect-tolerance strategy. A fully parameterized, detailed yield model for WASP devices is presented, and the implications of various design options for device yield are analyzed. The WASP architecture has been shown to be capable of yields well in excess of the target of 50% for 8192-APE WASP devices.<>