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1991 Proceedings, International Conference on Wafer Scale Integration最新文献

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Practical considerations for WSI based systems 基于WSI的系统的实际考虑
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151734
J. E. Brewer
{"title":"Practical considerations for WSI based systems","authors":"J. E. Brewer","doi":"10.1109/ICWSI.1991.151734","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151734","url":null,"abstract":"The author examines some aspects of the Westinghouse WSI (wafer scale integration) development effort. The status of device production efforts is summarized, important packaging-oriented practical issues are discussed, and a particular approach to WSI packaging is presented. Some critical issues associated with overall circuit density, power distribution, signal connections, and heat removal are identified.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114090648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Self-reconfigurable algorithm of WSI sorting network WSI排序网络的自重构算法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151723
S. Horiguchi, I. Numata, M. Kimura
{"title":"Self-reconfigurable algorithm of WSI sorting network","authors":"S. Horiguchi, I. Numata, M. Kimura","doi":"10.1109/ICWSI.1991.151723","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151723","url":null,"abstract":"The authors present a self-reconfigurable algorithm for a hierarchically redundant WSI (wafer scale integration) sorting network. This WSI sorting network consists of a mesh interconnection and a modified bitonic sorter with spare cells. The fault tolerance performance of the WSI sorting network using the self-reconfigurable algorithm is discussed. It is confirmed that the hierarchical redundancy of the WSI sorting network achieves a higher fault tolerance performance than a nonhierarchical network and is suitable for both clustered faults and random faults.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131129528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Yield evaluation of WSI parallel systems WSI并联系统成品率评价
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151710
N. Tzeng, C.-H. Chen
{"title":"Yield evaluation of WSI parallel systems","authors":"N. Tzeng, C.-H. Chen","doi":"10.1109/ICWSI.1991.151710","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151710","url":null,"abstract":"The authors propose a methodology for estimating the yield of WSI (wafer scale integration) parallel systems efficiently and accurately by taking advantage of the fact that most of the parallel systems have recursive structures by nature. This methodology evaluates yield by means of a recursive approach without enumerating all fixable states. It is often possible to derive the yield of WSI parallel systems (with recursive structures) of any size. Using this approach, the authors evaluate the exact yield of a fault-tolerant modular binary tree and the yield bounds of a reconfigurable cube-connected cycle structure.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131582771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect-tolerant implementation of a systolic array for two-dimensional convolution 二维卷积收缩数组的容错实现
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151691
K. Ronner, V. Hecht, P. Pirsch
{"title":"Defect-tolerant implementation of a systolic array for two-dimensional convolution","authors":"K. Ronner, V. Hecht, P. Pirsch","doi":"10.1109/ICWSI.1991.151691","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151691","url":null,"abstract":"A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural concepts for the design of large-area chips have been investigated and applied to the chip-design. Yield calculations show that, by the combination of new architectural concepts, effective hierarchical reconfiguration schemes, layout redundancies, and design of global parts using conservative design-rules, a high yield increase (67%) with low area overhead (6%) has been achieved.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128110526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The evolution of DRAM technology towards WSI DRAM技术向WSI的演进
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151721
K. Warren, A. Sinclair
{"title":"The evolution of DRAM technology towards WSI","authors":"K. Warren, A. Sinclair","doi":"10.1109/ICWSI.1991.151721","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151721","url":null,"abstract":"Issues connected with the evolution of dynamic random-access memory (DRAM) technology towards wafer scale integration (WSI) are examined. It is pointed out that as one moves towards submicron technologies, fundamental physical, electrical, and processing limits are being encountered, and it is becoming clear that this trend cannot continue. This phenomenon is most clearly demonstrated by the development of DRAM technology. The costs to develop new fabrication lines are escalating to levels that require funding investments approaching national rather that corporate budgets. It is concluded that it is these factors which make WSI and related high-density interconnect technologies an inevitability if demands for higher levels of circuit integration are to continue to be satisfied into the nineties and beyond.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"2527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluation of defect-tolerance scheme in a 600 M-bit wafer-scale memory 600 m位晶圆级存储器中缺陷容限方案的评价
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151690
K. Yamashita, S. Ikehara, M. Nagashima, T. Tatematsu
{"title":"Evaluation of defect-tolerance scheme in a 600 M-bit wafer-scale memory","authors":"K. Yamashita, S. Ikehara, M. Nagashima, T. Tatematsu","doi":"10.1109/ICWSI.1991.151690","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151690","url":null,"abstract":"Describes a simulator using Monte Carlo simulation that has been used to evaluate the defect tolerance scheme in 600 M-bit wafer-scale DRAM having additional switching register network logic (SW-REG). To obtain functional wafers even if a memory core yield is as low as 5%, a bypass line for SW-REG and spare lines for common signals are prepared, and the number of sections that the memory is to be partitioned into is determined. One can obtain about 300 to 650 M bits on a 6-in wafer when the memory core yield is 5 to 70%. Although the wafer-scale memory has hundreds of common signal lines because of parallel access, one can have an area-efficient system with optimized additional circuits using the simulator.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127913192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Yield enhancement of wafer scale integrated arrays 晶圆规模集成阵列的良率提升
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151713
J. Narasimhan, K. Nakajima, C. Rim, A. Dahbura
{"title":"Yield enhancement of wafer scale integrated arrays","authors":"J. Narasimhan, K. Nakajima, C. Rim, A. Dahbura","doi":"10.1109/ICWSI.1991.151713","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151713","url":null,"abstract":"In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on Computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. In the present work, the authors consider the problem of yield enhancement along the same lines as above not only for PGAs but also for wafer-scale-integrated arrays. A heuristic algorithm for reconfiguration based on a graph-theoretic formulation of the problem and a polynomial-time exact algorithm for a special case of the problem are presented. The reconfiguration algorithms are evaluated by comparing the routability and wire length of the reconfigured and initial placements of the circuit.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134476636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Limitations to the size of single-chip electronic neural networks 单片电子神经网络的尺寸限制
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151697
D. Feltham, Wojciech Maly
{"title":"Limitations to the size of single-chip electronic neural networks","authors":"D. Feltham, Wojciech Maly","doi":"10.1109/ICWSI.1991.151697","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151697","url":null,"abstract":"The authors analyze and quantify the design tradeoffs which will limit the size of single-chip analog neural networks implemented using standard CMOS technology. Issues investigated include the limits imposed by the neural network architectures themselves, and the related effects of processing variations and defects on the ultimate size of manufacturable neural systems. It is shown that neural networks, even if potentially fault-tolerant, will not automatically provide the capability to make limitless large single-chip integrated circuits.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114530150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Wafer scale integration-a technology whose time has come 晶圆规模集成技术的时代已经到来
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151735
P. Cavill, P. E. Stapleton, J. M. Wilkinson
{"title":"Wafer scale integration-a technology whose time has come","authors":"P. Cavill, P. E. Stapleton, J. M. Wilkinson","doi":"10.1109/ICWSI.1991.151735","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151735","url":null,"abstract":"The criteria which every new technological advance needs to satisfy before it can become accepted into the mainstream of product development are identified. it is then suggested that one company's wafer scale integration (WSI) now satisfies these criteria; it meets the needs of the intermediate storage market, and it is cost effective to manufacture because it provides a way for semiconductor manufacturers to achieve high yields quickly, without the need for additional capital expenditure. The product road map for WSI is described.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124909956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Interconnect and cell redundancy tradeoffs for WSI: an FFT case study WSI的互连和单元冗余权衡:FFT案例研究
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151733
D. Landis, H. Nienhaus, N. Nigam
{"title":"Interconnect and cell redundancy tradeoffs for WSI: an FFT case study","authors":"D. Landis, H. Nienhaus, N. Nigam","doi":"10.1109/ICWSI.1991.151733","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151733","url":null,"abstract":"The authors describe the results of an investigation into the relationship between cell redundancy, yield, and interconnect area for WSI (wafer scale integration) designs. A general analysis framework is presented which allows algorithmic computation of the optimum amount of redundancy from an area efficiency standpoint. The results of this theoretical study were applied to the case study of an 8-point FFT (fast Fourier transform) WSI design which uses a novel architecture requiring only two functional cell types. The optimum design point and predicted cell yield are identified for this case study.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129677875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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