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1991 Proceedings, International Conference on Wafer Scale Integration最新文献

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Large area defect-tolerant tree architectures 大面积容错的树型架构
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151706
W. Shi, W. Fuchs
{"title":"Large area defect-tolerant tree architectures","authors":"W. Shi, W. Fuchs","doi":"10.1109/ICWSI.1991.151706","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151706","url":null,"abstract":"The authors study the problem of designing large-area defect-tolerant tree architectures under the fault model that each processor, switch, and wire may be defective with independent constant probability. Using expander graphs, it is shown that, for any given constant 0<h<1, there is a design of n processors with layout area O(n) such that the harvest rate is asymptotically h, provided the yield of each switch and wire is above a constant threshold depending on h but independent of n. The significance of this result is that, under this fault model, all previous defect-tolerant tree architectures have a harvest rate that is asymptotically 0.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116637206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Structures for a configuration and self-configuration of WSI systems with a low degree of regularity 具有低规则度的WSI系统的组态和自组态结构
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151703
Hiroshi Iden
{"title":"Structures for a configuration and self-configuration of WSI systems with a low degree of regularity","authors":"Hiroshi Iden","doi":"10.1109/ICWSI.1991.151703","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151703","url":null,"abstract":"For WSI (wafer scale integration) systems with a low degree of regularity, a design strategy is investigated which features a self-configuration. Redundant arrangements of modules as well as implementations of subsidiary circuitry are presented. They provide a multiple defect tolerance even for central circuitry such as system control, test, and configuration circuitry. The components are implemented in a WSI system ( approximately 16 cm/sup 2/) which is still under production. Due to the modular nature of these components, they may be applied to other complex redundant systems. The efficiency of the proposed solutions is confirmed by the results of yield calculations.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125613966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Excimer laser formed vertical links of standard CMOS double-level metallizations 准分子激光形成标准CMOS双能级金属化的垂直链接
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151717
T. Hillmann-Ruge, H.-D. Hartmann
{"title":"Excimer laser formed vertical links of standard CMOS double-level metallizations","authors":"T. Hillmann-Ruge, H.-D. Hartmann","doi":"10.1109/ICWSI.1991.151717","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151717","url":null,"abstract":"Excimer-laser-formed vertical links between two metallization levels are demonstrated on special test chips, fabricated by ES2 in a standard CMOS process. Yield is 100% using link structures of 20 mu m*20 mu m and 14 mu m*14 mu m linear dimension and two identical laser pulses. Mean contact resistance is less than 200 Omega . A new test chip is built using sandwich layers for metallization and spin-on glass planarization. Temperature and humidity cycling of processed antifuses was carried out.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124541202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Guidelines for testing WSI sequential arrays 测试WSI顺序阵列的指南
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151731
G. Buonanno, D. Sciuto, Y.-N. Shen
{"title":"Guidelines for testing WSI sequential arrays","authors":"G. Buonanno, D. Sciuto, Y.-N. Shen","doi":"10.1109/ICWSI.1991.151731","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151731","url":null,"abstract":"New results on generating a functional test procedure for linear arrays composed of sequential cells are presented. The sequential cell is modeled as a finite state machine and the testing process is characterized by the definition of a test sequence for each transition of the finite state machine, by means of the unique input/output sequence technique. The two sets of conditions that are defined (for controllability and observability) allow testing of a one-dimensional sequential array in linear time. The methodology presented has been applied to a number of different examples of sequential linear arrays (convolvers, complex multipliers, and FFT arrays), and fault coverage obtained by considering the single stuck-at fault model was evaluated.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128617356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A WSI macrocell fault circumvention strategy 一种WSI宏小区故障规避策略
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151701
E. Swartzlander
{"title":"A WSI macrocell fault circumvention strategy","authors":"E. Swartzlander","doi":"10.1109/ICWSI.1991.151701","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151701","url":null,"abstract":"The use of a design paradigm that consists of a hierarchy of structures from cells to macrocells to functional elements to wafers greatly simplifies the design and development of wafer scale integration (WSI) systems. The authors examine the use of pooled spares, for fault circumvention at the macrocell level of the hierarchy. A method is provided that maximizes the yield of the pools of macrocells as a function of the yield of individual macrocells and the yield of the interconnection network. An example shows the application of this theory to a floating-point complex butterfly for signal processing applications.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115862282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
VHDL-based design and analysis of defect tolerant VLSI/WSI array architectures 基于vhdl的缺陷容忍度VLSI/WSI阵列架构设计与分析
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151711
S. Kuo, K. Wang
{"title":"VHDL-based design and analysis of defect tolerant VLSI/WSI array architectures","authors":"S. Kuo, K. Wang","doi":"10.1109/ICWSI.1991.151711","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151711","url":null,"abstract":"Presents an integrated computer-aided design environment, the VAR (VHDL-based array reconfiguration) system, for the design, diagnosis, reconfiguration, simulation, and evaluation of an array architecture described in VHDL. VAR allows one to study fault diagnosis and reconfiguration algorithms by inserting user-defined faults into the array and then locating the faulty processing elements as well as simulating the actual reconfiguration process by mapping a target array onto a host array. Thus, VAR can assist the designer in evaluating different combinations of diagnosis algorithms, reconfiguration algorithms, and reconfigurable architectures.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"260 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127557180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 80 MHz digital signal processing multichip module made with the General Electric high density interconnect technology 采用通用电气高密度互连技术制造的80mhz数字信号处理多芯片模块
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151715
M. Gdula, K. Welles, R. Wojnarowski
{"title":"An 80 MHz digital signal processing multichip module made with the General Electric high density interconnect technology","authors":"M. Gdula, K. Welles, R. Wojnarowski","doi":"10.1109/ICWSI.1991.151715","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151715","url":null,"abstract":"A unique packaging and interconnect technology was used to build a multichip, four CPU element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed-circuit-board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132976795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfiguration of binary trees: the flow-driven approach 二叉树的重构:流驱动的方法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151708
A. Antola, N. Scarabottolo
{"title":"Reconfiguration of binary trees: the flow-driven approach","authors":"A. Antola, N. Scarabottolo","doi":"10.1109/ICWSI.1991.151708","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151708","url":null,"abstract":"A novel reconfiguration technique for defect and fault tolerance in binary trees is presented. The reconfiguration scheme, based on spare elements distributed inside the tree, allows one to increase the probability of reconfiguration, resulting in an extremely reliable final structure. Quantitative evaluations of the effectiveness of the reconfiguration technique (i.e. probability of surviving different numbers of faults) and of the reliability of the redundant trees are given.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133463777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfiguring processor arrays using multiple-track models 使用多轨道模型重新配置处理器阵列
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151732
T. Varvarigou, V. Roychowdhury, T. Kailath
{"title":"Reconfiguring processor arrays using multiple-track models","authors":"T. Varvarigou, V. Roychowdhury, T. Kailath","doi":"10.1109/ICWSI.1991.151732","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151732","url":null,"abstract":"The authors study a 3-track-1-spare model that has three tracks along each channel and one spare row or column along each boundary. It is shown that the model uses the spare processors very efficiently; specifically, it is proved that a 3-track-1-spare model can support any set of nonintersecting compensation paths. This provides theoretical justification of the observations made in the literature about the power of 3-track models. The authors also discuss efficient algorithms for reconfiguration in the 3-track-1-spare model and show that it has much higher reconfiguration probability than the corresponding 2 1/2-track-2-spare model.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123348338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A variable domain approach to reconfiguration of WSI processor arrays WSI处理器阵列重构的可变域方法
1991 Proceedings, International Conference on Wafer Scale Integration Pub Date : 1991-01-29 DOI: 10.1109/ICWSI.1991.151707
P. K. Rhee, J.H. Kim
{"title":"A variable domain approach to reconfiguration of WSI processor arrays","authors":"P. K. Rhee, J.H. Kim","doi":"10.1109/ICWSI.1991.151707","DOIUrl":"https://doi.org/10.1109/ICWSI.1991.151707","url":null,"abstract":"A novel reconfiguration algorithm for WSI (wafer scale integration) processor arrays using the concept of a variable domain is discussed. Variable domain is decided based on a fault distribution. The algorithm utilizes fault distribution information in the global assignment phase as well as in the local assignment phase. The concept of variable domain used in the algorithm overcomes the weakness of fixed domain approaches in the presence of clustered faulty cells. The number of faulty cells to be tolerated need not be predefined; thus a logical array maximizes the dimension from a given faulty physical array.<<ETX>>","PeriodicalId":413164,"journal":{"name":"1991 Proceedings, International Conference on Wafer Scale Integration","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116934260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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