WSI interconnect issues: practical experience gained on the WASP project

Abstract

The problems of external interfacing and internal interconnection for WSI (wafer scale integration) devices are considered. In particular, the WASP (WSI associative string processor) 2A device is examined in detail, and practical results are presented. Analysis of the experimental on-wafer interconnection included on WASP 2A has shown that, given simple layout precautions, a high yield can be obtained for non-defect-tolerant buses. However, it is also apparent that practical experience concerning the defect modes of these buses is important in the design of any defect tolerance strategy for yield improvement. Results from using WASP 2A have shown that defect and fault tolerance may be cost-effectively implemented at the level of the wafer interface, allowing for the recovery from defects and in-service failures, and substantially increasing the projected yield of this crucial wafer component.<>