Defect tolerance and yield for a wafer scale FFT processor system

Abstract

A wafer scale system for frame-by-frame computation of the fast Fourier-transform (FFT) is described. It is based on an eight-point FFT wafer design, which uses two types of cells, a multiply-subtract-add (MSA) cell and a coefficient ROM cell. Systematic repetition of these cells and the interconnect forms the physical wafer. The cells are designed for high performance and testability. For successive 512-point frames, the throughput is estimated at 20 million samples/s. Innovations in preplacement have reduced the traffic in the interconnect channels while enhancing the reconfigurability in the presence of defects. Estimates of wafer yield using a new model for harvesting probability are also presented.<>