Multiple voting systolic array

Abstract

A model of the multiple voting systolic array is proposed. The proposed fault tolerant technique uses majority decision by voting, without reconfiguration. As an example, a DFT (discrete Fourier transform) implementation of a triple voting systolic array is presented. It is shown that area redundancy is small and dynamic fault recovery is possible. It is believed that proposed fault-tolerant architecture is suitable for WSI (wafer-scale integration) processors.<>