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Mixer-First Extremely Wideband 43–97 GHz RX Frontend with Broadband Quadrature Input Matching and Current Mode Transformer-Based Image Rejection for Massive MIMO Applications 混合优先的极宽带43-97 GHz RX前端与宽带正交输入匹配和基于电流模式互感器的图像抑制大规模MIMO应用
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075896
Amr Ahmed, Min-Yu Huang, Hua Wang
{"title":"Mixer-First Extremely Wideband 43–97 GHz RX Frontend with Broadband Quadrature Input Matching and Current Mode Transformer-Based Image Rejection for Massive MIMO Applications","authors":"Amr Ahmed, Min-Yu Huang, Hua Wang","doi":"10.1109/CICC48029.2020.9075896","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075896","url":null,"abstract":"This work presents an ultra-wideband mixer-first front-end that can cover mmWave communications bands in the frequency range 43–97 GHz. The front-end employs a mmWave 90°coupler as an input stage in order to achieve wideband matching and RF quadrature signal generation. Passive mixer and multi-gated gm3-cancellation IF amplifiers used to achieve and maintain high linearity across the frequency range. In addition, the frond-end implements a current mode image rejection using a transformer based IF 90°coupler. The receiver front-end is implemented in CMOS 22nm FD-SOI technology and achieves an ultra-wideband S11 matching while employing up to 32 dB image rejection and 1.6-5.2 dBm in-band IIP3. In addition, the front-end supports up to 6 Gbps 64QAM modulated data.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"129 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS 一种60gb /s PAM4有线接收机，采用28nm CMOS跟踪和再生切片器，具有2分频直接决策反馈均衡
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075948
Kuan-Chang Chen, W. Kuo, A. Emami-Neyestanak
{"title":"A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS","authors":"Kuan-Chang Chen, W. Kuo, A. Emami-Neyestanak","doi":"10.1109/CICC48029.2020.9075948","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075948","url":null,"abstract":"This paper describes a 4-level pulse-amplitude modulation (PAM4) wireline receiver incorporating a continuous time linear equalizer (CTLE) and a 2-tap direct decision feedback equalizer (DFE). A track-and-regenerate CMOS slicer is proposed and employed in the PAM4 receiver. The reduced delay of the proposed slicer and its full-swing outputs allow the implementation of 2-tap direct decision-feedback equalization at 60-Gb/s with improved energy efficiency and area requirements. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieved BER better than 1E-12 at 60-Gb/s with 1.1 pJ/b energy efficiency measured over a channel of 8.2dB loss at Nyquist rate.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133632600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 760 nW, 180 nm CMOS Analog Voice Activity Detection System 一个760 nW, 180 nm CMOS模拟语音活动检测系统
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075954
M. Croce, Brian W. Friend, F. Nesta, L. Crespi, P. Malcovati, A. Baschirotto
{"title":"A 760 nW, 180 nm CMOS Analog Voice Activity Detection System","authors":"M. Croce, Brian W. Friend, F. Nesta, L. Crespi, P. Malcovati, A. Baschirotto","doi":"10.1109/CICC48029.2020.9075954","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075954","url":null,"abstract":"This paper presents a fully analog, signal-to-noise ratio (SNR) based voice-activity detection circuit, which achieves 99.5 % classification accuracy in a domestic environment in the presence of loud ambient noise, consuming 760 nW from a 1.2 V supply. The circuit exploits an energy-efficient analog implementation with continuous-time non-linear operation and fully-passive switched-capacitor processing, to minimize both the power consumption and the chip area. The VAD circuit prototype, fabricated in a 180 nm CMOS technology, occupies 0.14mm2.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-die Integration Using Advanced Packaging Technologies 采用先进封装技术的多模集成
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075901
Hyung-Jin Lee, R. Mahajan, F. Sheikh, R. Nagisetty, Manish Deo
{"title":"Multi-die Integration Using Advanced Packaging Technologies","authors":"Hyung-Jin Lee, R. Mahajan, F. Sheikh, R. Nagisetty, Manish Deo","doi":"10.1109/CICC48029.2020.9075901","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075901","url":null,"abstract":"This paper presents a review of 2-D and 3-D multi-die integration technologies and focuses on on-package multi-die co-integration to create new types of system platforms. These dice may or may not be implemented in the same technology process. The paper first presents the challenges of process scaling and coexistence of logic, IO, and RF, and discusses new system/platform requirements from emerging applications. Following the motivation, a review of multi-die integration technologies with a focus on-package 2-D and 3-D multi-die integration and process enhancements for its support is provided. Finally, we present three new multi-die platforms which embody recent innovations in system platform integration to create new FPGA and CPU architectures which can be used to efficiently implement AI, HPC, and machine learning algorithms.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116515088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology 基于22nm FinFET CMOS技术的0.5 v ~ 0.9 v、0.2 ghz ~ 5ghz锁相时间小于200ns的超低功耗数字辅助模拟环锁相环
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075897
Bo Xiang, Yongping Fan, J. Ayers, James Shen, Dan Zhang
{"title":"A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology","authors":"Bo Xiang, Yongping Fan, J. Ayers, James Shen, Dan Zhang","doi":"10.1109/CICC48029.2020.9075897","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075897","url":null,"abstract":"This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop (PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of 0.213mW/GHz and FoM of -234.4dB at. 08V supply with only 200ns lock time at 100MHz reference clock. All the components are using a single supply voltage and it can operate from 0.5V to 0.9V supply with a wide output clock frequency range from 0.2GHz to 5GHz. At 0.5V supply, it can support 1.6GHz operation with very high power efficiency of 0.08m W/GHz. It can also support a wide reference clock frequency range from 20MHz to 200MHz. This low power design is suitable for System-on-Chip (SoC) and Internet-of- Things (IoT) processors.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124624213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited) 连续时间带通δ - σ调制器和比特流处理:(特邀)
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075928
M. Flynn, J. Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell
{"title":"Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited)","authors":"M. Flynn, J. Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell","doi":"10.1109/CICC48029.2020.9075928","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075928","url":null,"abstract":"Continuous- Time Bandpass Delta-Sigma Modulators (CTBPDSMs) are effective for IF sampling and simplify receiver design. Bitstream processing (BSP) can be combined with an array of CTBPDSMs to enable highly area and power efficient digital beamforming. BSP directly processes the raw bit-stream outputs of the quantizers, enabling digital processing with simple MUXs. The combination of BSP and CTBPDSMs is also effective in a digital PLL. Emerging techniques show the promise of multi-band noise-shaping in a CTDSM.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122794245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices 一种用于安全植入式设备的低功耗双因素认证单元
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075945
Saurav Maji, Utsav Banerjee, Samuel H. Fuller, Mohamed R. Abdelhamid, P. Nadeau, R. Yazicigil, A. Chandrakasan
{"title":"A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices","authors":"Saurav Maji, Utsav Banerjee, Samuel H. Fuller, Mohamed R. Abdelhamid, P. Nadeau, R. Yazicigil, A. Chandrakasan","doi":"10.1109/CICC48029.2020.9075945","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075945","url":null,"abstract":"This paper presents a dual-factor authentication protocol and its low-power implementation for security of implantable medical devices (IMDs). The protocol incorporates traditional cryptographic first-factor authentication using Datagram Transport Layer Security - Pre-Shared Key (DTLS-PSK) followed by the user's touch-based voluntary second-factor authentication for enhanced security. With a low-power compact always-on wake-up timer and touch-based wake-up circuitry, our test chip consumes only 735 pW idle state power at 20.15 Hz and 2.5 V. The hardware accelerated dual-factor authentication unit consumes 8 µW at 660 kHz and 0.87 V. Our test chip was coupled with commercial Bluetooth Low Energy (BLE) transceiver, DC-DC converter, touch sensor and coin cell battery to demonstrate standalone implantable operation and also tested using in-vitro measurement setup.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114156217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A10.13uJ/classification 2-channel Deep Neural Network-based SoC for Emotion Detection of Autistic Children 基于分类2通道深度神经网络的自闭症儿童情绪检测
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075952
Abdul Rehman Aslam, Talha Iqbal, Mahnoor Aftab, Wala Saadeh, Muhammad Awais Bin Altaf
{"title":"A10.13uJ/classification 2-channel Deep Neural Network-based SoC for Emotion Detection of Autistic Children","authors":"Abdul Rehman Aslam, Talha Iqbal, Mahnoor Aftab, Wala Saadeh, Muhammad Awais Bin Altaf","doi":"10.1109/CICC48029.2020.9075952","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075952","url":null,"abstract":"An EEG-based noninvasive neuro-feedback SoC for emotion classification of Autistic children is presented. The AFE comprises two entirely shared EEG-channels using sampling capacitors to reduce the area by 30% and achieve an overall integrated input-referred noise of 0.55µ VRMS with cross-talk of - 79dB. The 4-layers Deep Neural Network (DNN) classifier is integrated on-sensor to classify (4 emotions) with >85% accuracy. The 16mm2 SoC in 0.18um CMOS consumes 10.13µJ/classification for 2 channels.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Doping of Aluminum Nitride and the Impact on Thin Film Piezoelectric and Ferroelectric Device Performance 氮化铝的掺杂及其对薄膜压电和铁电器件性能的影响
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075911
R. Olsson, Zichen Tang, Michael D’Agati
{"title":"Doping of Aluminum Nitride and the Impact on Thin Film Piezoelectric and Ferroelectric Device Performance","authors":"R. Olsson, Zichen Tang, Michael D’Agati","doi":"10.1109/CICC48029.2020.9075911","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075911","url":null,"abstract":"Recently, the substitutional doping of scandium (Sc) for aluminum (Al) to form aluminum scandium nitride (AlScN) has been studied to enhance the piezoelectric properties and introduce ferroelectric properties into aluminum nitride (AlN) based material systems. The properties achieved to date have profound implications for the performance of piezoelectric filters, and energy harvesters, and for scaling the bit density of ferroelectric memories. This paper reviews the piezoelectric and ferroelectric performance that has been demonstrated, and the impact of the material properties on the performance of piezoelectric and ferroelectric devices.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117279227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 0.5-3 GHz I/Q Interleaved Direct-Digital RF Modulator with up to 320 MHz Modulation Bandwidth in 40 nm CMOS 一个0.5- 3ghz的I/Q交错直接数字射频调制器，在40nm CMOS调制带宽高达320mhz
2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075949
Yiyu Shen, R. Bootsman, M. Alavi, L. D. Vreede
{"title":"A 0.5-3 GHz I/Q Interleaved Direct-Digital RF Modulator with up to 320 MHz Modulation Bandwidth in 40 nm CMOS","authors":"Yiyu Shen, R. Bootsman, M. Alavi, L. D. Vreede","doi":"10.1109/CICC48029.2020.9075949","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075949","url":null,"abstract":"This paper presents a wideband, $2times 12$ -bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology. The proposed digital-intensive quadrature upconverter features an advanced I/Q-mapping unit cell to boost RF power, in-band linearity, and out-of-band spectral purity. The modulator provides more than 14 dBm RF peak output power. It achieves an ACLR of -52 dBc and an EVM of -40 dB when applying a 20 MHz 256 QAM signal at 2.4 GHz. When applying a 320 MHz 256 QAM signal at 2.4 GHz, the measured ACLR and EVM are better than -43 dBc and -32 dB, respectively, without applying any digital pre-distortion.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126255318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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