A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology

Abstract

This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop (PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of 0.213mW/GHz and FoM of -234.4dB at. 08V supply with only 200ns lock time at 100MHz reference clock. All the components are using a single supply voltage and it can operate from 0.5V to 0.9V supply with a wide output clock frequency range from 0.2GHz to 5GHz. At 0.5V supply, it can support 1.6GHz operation with very high power efficiency of 0.08m W/GHz. It can also support a wide reference clock frequency range from 20MHz to 200MHz. This low power design is suitable for System-on-Chip (SoC) and Internet-of- Things (IoT) processors.