2020 IEEE Custom Integrated Circuits Conference (CICC)最新文献_第2页

A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity 一种6-8GHz多通道可重构脉冲收发器，具有3.5ns处理延迟和1cm测距精度，用于安全无线连接

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075925

Haixin Song, W. Rhee, Zhihua Wang

引用次数: 0

Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial 多位反馈A/D转换器中DAC非线性的数字校正:特邀讲座

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075916

P. Payandehnia, Tao He, Yanchao Wang, G. Temes

引用次数: 4

HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis HL5:一种32位RISC-V高级综合处理器

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075913

Paolo Mantovani, R. Margelli, Davide Giri, L. Carloni

引用次数: 5

A Wide Output Voltage Range Single-Input-Multi-Output Hybrid DC-DC Converter Achieving 87.5% Peak Efficiency With a Fast Response Time and Low Cross Regulation for DVFS Applications 宽输出电压范围单输入多输出混合DC-DC变换器，峰值效率87.5%，响应时间快，低交叉调节，适用于DVFS应用

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075892

Zhiyuan Zhou, Nghia Tang, Bai Nguyen, Wookpyo Hong, P. Pande, D. Heo

引用次数: 6

Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects 内存计算与新兴的非易失性存储器:挑战与展望

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075887

Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang

引用次数: 37

Design and Optimization of Low Power and Low Light Sensor: (Invited) 低功耗低光传感器的设计与优化:(特邀)

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075874

Assim Boukhayma, Antonino Caizzone, Raffaele Capoccia, C. Enz

{"title":"Design and Optimization of Low Power and Low Light Sensor: (Invited)","authors":"Assim Boukhayma, Antonino Caizzone, Raffaele Capoccia, C. Enz","doi":"10.1109/CICC48029.2020.9075874","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075874","url":null,"abstract":"The current trend towards embedding more and more light sensors in portable and wearable devices is calling for higher integration and reuse of the sensor interface electronics. In many applications, the light needs to be generated locally, which becomes the dominant source of power consumption. Power can hence be saved by making the sensor more sensitive to lower light. At low light the noise is totally dominated by the noise coming from the electronic readout chain. This paper shows how this noise can be minimized all along the readout chain, from the pixel to the ADC. It also shows that many low-light applications actually share the same readout architecture. The latter is made of the pixel including a source follower, a shared amplifier and a correlated double sampling (CDS) or correlated multiple sampling (CMS) stage that is key for eliminating the low-frequency noise and reducing the white noise for CMS. It is shown how each of these building blocks can be optimized for reaching a minimum input-referred noise. The design methodology is then illustrated by three applications, including a 0.5 etectonrms., CMOS VGA imager, a 2.6 µW PPG sensor and a 10 µW 1D time-of-flight distance ranging device.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125284006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology 利用单极TFT技术实现节能、全摆幅解码器

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075893

Qing Li, Czang-Ho Lee, W. Wong, M. Sachdev

引用次数: 1

A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in 通过热载流子注入老化实现了0.5 v 2.07 fj /b 497-F2 EE/CMOS混合SRAM物理不可克隆功能，误码率< 1E-7

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075875

Kunyang Liu, Hongliang Pu, H. Shinohara

{"title":"A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in","authors":"Kunyang Liu, Hongliang Pu, H. Shinohara","doi":"10.1109/CICC48029.2020.9075875","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075875","url":null,"abstract":"This paper presents a bit-error free SRAM-based physically unclonable function (PUF) in 130-nm standard CMOS. The PUF has a compact bitcell, with a bitcell area of 497 F2. It switches from EE SRAM to CMOS SRAM mode during evaluation, achieving high native stability, low-voltage evaluation, and low-power operation. Its stability is reinforced to 100% through hot carrier injection (HCI) burn-in on the alternate-direction nMOS load, which causes no visible oxide damage and does not require additional fabrication processes or extra transistors in the bitcell. Experimental results show that the prototype chips achieved actual zero bit error across 0.5-0.7 V and -40°C to 120 °C, as well as zero error (<1E-7 BER) at the worst VT corner after accelerated aging test equivalent to ~21 years of operation. The PUF functions stably down to 0.5 V, with an energy of 2.07 fJ/b, which includes both the evaluation and read-out power. The secure, compact, low-power and 100% stable features of the PUF make it an excellent candidate for the resource-constrained Internet of Things security.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123237557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations 用于自供电物联网soc的亚微安培能量收集和电源管理单元:模拟与数字实现

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075879

Shuo Li, B. Calhoun

{"title":"Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations","authors":"Shuo Li, B. Calhoun","doi":"10.1109/CICC48029.2020.9075879","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075879","url":null,"abstract":"The power consumption of ultra-low-power (ULP) Internet-of-Things (IoT) SoCs and components has been scaling down from µW to pW levels over the past ten years. Designing energy harvesting and power management units (EH-PMUs) that consume sub-µA quiescent current to efficiently provide such low load current is challenging. This paper reviews the trends and techniques for sub-µA EH-PMUs with a specific focus on the choice between analog and digital implementations. We first discuss ULP EH-PMU design trends based on recent published results and then analyze three design examples. The first example reviews a popular multiple-input multiple-output (MIMO) EH-PMU architecture with ultra-low quiescent current and compares tradeoffs for analog vs. digital zero-current detectors. The second example discusses the design of analog and digital low-dropout regulators (LDOs) with a performance comparison from silicon measurement results. The digital LDO can achieve faster settling time for step response than the analog structure, but the analog LDO has no ripple, making it ideal for noise-sensitive blocks like RF. Finally, an analog power monitor for maximum-power-point tracking (MPPT) in a piezoelectric energy harvester utilizes subthreshold transistor characteristics to simply a complex algorithm and to maintain low power consumption.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125509563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping 具有增强级间增益误差整形和量化误差整形的77.1 db 6.25 mhz - bw管道SAR ADC

2020 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2020-03-01 DOI: 10.1109/CICC48029.2020.9075905

Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, R. Xu, Abhishek Mukherjee, T. Andeen, Nan Sun

引用次数: 3