{"title":"一种6-8GHz多通道可重构脉冲收发器,具有3.5ns处理延迟和1cm测距精度,用于安全无线连接","authors":"Haixin Song, W. Rhee, Zhihua Wang","doi":"10.1109/CICC48029.2020.9075925","DOIUrl":null,"url":null,"abstract":"This paper describes a communication/ranging pulse-based transceiver that enables physical-layer security against relay attack. A reconfigurable transceiver system with concatenation operation is designed by having PPM/PWM-based two-bit communication between the prover and the verifier, significantly reducing the processing latency of the prover. Multichannel transmission with enhanced spectral efficiency and link margin are realized with channel hopping and subband hopping methods. A prototype 6-8GHz UWB/VWB transceiver is implemented in 65nm CMOS. The transceiver achieves a processing latency of <3.5ns for the prover and an RMS ranging accuracy of 1.0cm for the verifier, consuming 8.3mW with -73dBm sensitivity at 5Mb/$s$.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity\",\"authors\":\"Haixin Song, W. Rhee, Zhihua Wang\",\"doi\":\"10.1109/CICC48029.2020.9075925\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a communication/ranging pulse-based transceiver that enables physical-layer security against relay attack. A reconfigurable transceiver system with concatenation operation is designed by having PPM/PWM-based two-bit communication between the prover and the verifier, significantly reducing the processing latency of the prover. Multichannel transmission with enhanced spectral efficiency and link margin are realized with channel hopping and subband hopping methods. A prototype 6-8GHz UWB/VWB transceiver is implemented in 65nm CMOS. The transceiver achieves a processing latency of <3.5ns for the prover and an RMS ranging accuracy of 1.0cm for the verifier, consuming 8.3mW with -73dBm sensitivity at 5Mb/$s$.\",\"PeriodicalId\":409525,\"journal\":{\"name\":\"2020 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"97 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC48029.2020.9075925\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC48029.2020.9075925","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity
This paper describes a communication/ranging pulse-based transceiver that enables physical-layer security against relay attack. A reconfigurable transceiver system with concatenation operation is designed by having PPM/PWM-based two-bit communication between the prover and the verifier, significantly reducing the processing latency of the prover. Multichannel transmission with enhanced spectral efficiency and link margin are realized with channel hopping and subband hopping methods. A prototype 6-8GHz UWB/VWB transceiver is implemented in 65nm CMOS. The transceiver achieves a processing latency of <3.5ns for the prover and an RMS ranging accuracy of 1.0cm for the verifier, consuming 8.3mW with -73dBm sensitivity at 5Mb/$s$.