HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis

Abstract

The growing complexity of system-on-chip fuels the adoption of high-level synthesis (HLS) to reduce the design time of application-specific accelerators. General-purpose processors, however, are still designed using RTL and logic synthesis. Yet they are the most complex components of most systems-on-chip. We show that HLS can simplify the design of processors while enhancing their customization and reusability. We present HL5 as the first 32-bit RISC-V microprocessor designed with SystemC and optimized with a commercial HLS tool. We evalute HL5 through the execution of software programs on an experimental infrastructure that combines FPGA emulation with a standard RTL synthesis flow for a commercial 32 nm CMOS technology. By describing the challenges and opportunities of applying HLS to processor design, our paper aims also at sparking a renewed interest in HLS research.