2016 International Great Lakes Symposium on VLSI (GLSVLSI)最新文献_第6页

ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system 用ASIC实现的全数字自适应PVTA变差感知时钟生成系统

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903006

J. Perez-Puigdemont, F. Moll

引用次数: 2

Optimizing the operating voltage of tunnel FET-based SRAM arrays equipped with read/write assist circuitry 具有读写辅助电路的隧道场效应晶体管SRAM阵列的工作电压优化

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903031

H. Afzali-Kusha, A. Shafaei, Massoud Pedram

{"title":"Optimizing the operating voltage of tunnel FET-based SRAM arrays equipped with read/write assist circuitry","authors":"H. Afzali-Kusha, A. Shafaei, Massoud Pedram","doi":"10.1145/2902961.2903031","DOIUrl":"https://doi.org/10.1145/2902961.2903031","url":null,"abstract":"This paper deals with obtaining the minimum operating voltage of memory arrays based on TFET SRAM cells. First, we compare the I-V characteristics of two TFETs and one FDSOI using SPICE simulations. The results reveal that TFET devices exhibit high ON/OFF current ratios at different power supply voltage levels. This observation suggests a higher stability for SRAM cells based on these devices. Next, the characteristics of 6T SRAM cells implemented using minimum sized transistors based on these three device structures are compared. The comparison, which considers two TFET cell structures, i.e., inward and outward SRAMs, is performed at different supply voltages. The results for the hold static noise margin show that at low supply voltages (i.e., below 300mV), the FDSOI SRAM cell cannot hold data whereas both the inward and outward structures of TFET have acceptable noise margins at all supply voltages. Among the two TFET structures, the outward cell is selected because of higher speed especially for the write operation. TFET SRAMs suffer from long read access latency at ultra-low supply voltages (e.g., 150mV). The problem, however, may be overcome by using the negative GND read-assist technique. The results show that for a 32×32 TFET outward SRAM array, the minimum energy consumption (energy-delay product) may be achieved at the supply voltage of 200mV (300mV) with 1.32GHz (4.55GHz) as the read access frequency.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Leakage power minimization in deep sub-micron technology by exploiting positive slacks of dependent paths 利用相关路径的正松弛实现深亚微米技术的泄漏功率最小化

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902991

T. Chakraborty, Santanu Kundu, D. Agrawal, Sanjay Shinde, Jacob Mathews, R. K. James

{"title":"Leakage power minimization in deep sub-micron technology by exploiting positive slacks of dependent paths","authors":"T. Chakraborty, Santanu Kundu, D. Agrawal, Sanjay Shinde, Jacob Mathews, R. K. James","doi":"10.1145/2902961.2902991","DOIUrl":"https://doi.org/10.1145/2902961.2902991","url":null,"abstract":"Leakage power minimization is one of the key aspects of modern multi-million low power system-on-chip (SoC) design. In post timing-closure phase, leakage-in-place-optimization (LIPO) is generally adopted to reduce leakage power by swapping high-leaky cells in the timing-data-paths by low-leaky ones of the same footprint. The traditional LIPO does not touch the clock network for leakage recovery. This paper investigates the opportunity to reduce leakage power further of an already leakage-power-minimized (by LIPO), timing closed design by minimally altering the balanced clock tree. The proposed method, Opportunistic LIPO, intends to borrow unused positive-slack from downstream (and/or upstream) paths, may or may not be at immediate neighborhood, and provide a “positive skew” (and/or “negative skew”) at the capture (and/or launch) clock edge of the current path. In this way, the proposed scheme creates an opportunity in the current path to increase the low-leaky cells distribution. Experimental results, computed over some practical duration (less than 48 hours), on some industry-standard design based on 28nm technology, of having around 50 million gates, shows that the proposed algorithm, “Opportunistic LIPO”, achieves 10-30% better leakage power as compared to traditional LIPO without increasing the number of timing violations and having no significant impact on overall area.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A novel on-chip impedance calibration method for LPDDR4 interface between DRAM and AP/SoC 一种新的DRAM与AP/SoC之间LPDDR4接口的片上阻抗校准方法

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902982

Yongsuk Choi, Yong-Bin Kim

{"title":"A novel on-chip impedance calibration method for LPDDR4 interface between DRAM and AP/SoC","authors":"Yongsuk Choi, Yong-Bin Kim","doi":"10.1145/2902961.2902982","DOIUrl":"https://doi.org/10.1145/2902961.2902982","url":null,"abstract":"In this paper, a novel on-chip impedance calibration methodology for a LPDDR4 (low power double data rate) application is proposed. The background calibration operates to compensate mismatches and variations of the output NMOS drivers from process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect output driver transistor mismatches due to process and temperature variations. In addition, digitized sensor outputs from ADCs are used as inputs of look-up tables, which control calibration codes of the transmitter driver. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a standard 180nm CMOS technology, and the impedance calibration technique is demonstrated with external termination resistance of 40/48/60/80/120/240 ohm, respectively. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL (low voltage swing termination logic) signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to control the gain factor of the receiver. The active area including power-ring of the transmitter is 14.4mm2 with only 0.48mm2 of the proposed calibration circuit overhead.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114686119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Computing complex functions using factorization in unipolar stochastic logic 用单极随机逻辑分解计算复函数

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902999

Yin Liu, K. Parhi

引用次数: 6

High-speed polynomial multiplier architecture for ring-LWE based public key cryptosystems 基于环lwe的公钥密码体制的高速多项式乘法器结构

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902969

Chaohui Du, Guoqiang Bai, Xingjun Wu

引用次数: 22

VLSI design methods for low power embedded encryption 低功耗嵌入式加密的VLSI设计方法

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2902963

I. Verbauwhede

引用次数: 5

Modeling and study of two-BDT-nanostructure based sequential logic circuits 基于双bdt纳米结构的顺序逻辑电路建模与研究

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903001

P. Marthi, Sheikh Rufsan Reza, N. Hossain, J. Millithaler, M. Margala, I. Íñiguez-de-la-Torre, J. Mateos, T. González

{"title":"Modeling and study of two-BDT-nanostructure based sequential logic circuits","authors":"P. Marthi, Sheikh Rufsan Reza, N. Hossain, J. Millithaler, M. Margala, I. Íñiguez-de-la-Torre, J. Mateos, T. González","doi":"10.1145/2902961.2903001","DOIUrl":"https://doi.org/10.1145/2902961.2903001","url":null,"abstract":"In this paper, study of different digital logic circuits developed using two-BDT ballistic nanostructure is presented. New D flipflop (DFF) based on the same nanostructure is also proposed. The logic structure comprises two ballistic deflection transistors (BDTs) that are experimentally proven to operate at Terahertz frequencies. The non-linear behavior of the BDT's transfer characteristic has been perfectly reproduced by means of Monte Carlo simulations, where a specific attention has been devoted to surface charges. An analytical model built on the results of advanced MC simulations has been integrated into a behavioral Verilog AMS module to confirm the functionality of the circuit design. The module is used to analyze operating conditions of different combinational circuits and to investigate the feasibility of DFF design using BDT nanostructure. The simulation results indicate successful operation of both combinational and sequential circuits developed using two-BDT logic structure under proper biasing of gate and source terminals. The operating voltages of the proposed DFF are estimated to be ± 225mV.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A clockless sequential PUF with autonomous majority voting 具有自主多数投票的无时钟顺序PUF

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903029

Xiaolin Xu, Daniel E. Holcomb

引用次数: 11

Security primitive design with nanoscale devices: A case study with resistive RAM 纳米级器件的安全原语设计:电阻式RAM的案例研究

2016 International Great Lakes Symposium on VLSI (GLSVLSI) Pub Date : 2016-05-18 DOI: 10.1145/2902961.2903042

Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, S. Bhunia

引用次数: 11